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a AD1821 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 world wide web site: http://www.analog.com fax: 617/326-8703 ? analog devices, inc., 1997 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. modio? soundcomm ? * host signal processing codec features general compatible with microsoft ? pc 97 logo requirements supports applications written for windows ? 95, windows 3.1, windows nt, soundblaster ? pro, adlib ? /opl3 ? isa plug and play compatible operation from +5 v supply power management modes 100-lead pqfp package modem v.34bis (14.4 kbps up to 33.6 kbps) 56k software upgradable v.32/32bis, v.23, v.22/22bis, v.21, bell 103 and bell 212 modem protocols: v.8 and automode v.42/42bis mnp 5 data compression and v.43 mnp 2C4 error correction virtual com port 460.8 kbps and 16550 uart hayes at command set fax group 3, class 1 support v.17 (14.4 kbps), v.29 (9600/7200 bps), v.27/v.27ter hayes at command set ties escape sequence voice/telephony at#v commands unimodem v tapi-compliant voice/fax/modem distinction ring detection *soundcomm is a registered trademark of analog devices, inc. *phat is a trademark of analog devices, inc. all other trademarks are the property of their respective holders. functional block diagram m a i 2 s serial port (0) digital pll g = gain a = attenuate m = mute mv = master volume AD1821 xtali xtalo vol_dn vol_up midi_in midi_out a_1 b_1 a_x b_x a_2 b_2 a_y b_y mdm_in/ phone_in mic line synth cd vid l_out mdm_out/ r_out pclko sdata (1) lrclk (1) bclk (1) sdata (0) lrclk (0) bclk (0) iow ior dack (x) aen pc_a (15:0) pc_d (7:0) irq (x) drq (x) sdi sdo sclk i 2 s serial port (1) format fifo plug and play isa bus parallel interface format fifo 16-bit a/d converter pga selector mpu-401 wss/ sb pro register game port hardware volume control agc 0db/ 20db oscillators 16-bit d/a converter g a m phat stereo mv mv dsp serial port g a m g a m g a m sdfs data clk e 2 prom control sel xirq modem/ logical device control a m mv m a m a m a 2 2 2 2 2 phone_out phat stereo serial port interface music synthesizer g a m
AD1821 C2C rev. 0 on/off hook control call progress monitor dtmf detection and generation auto dial call forwarding and conferencing vox (voice detection) adpcm (32 kpbs voice compression) caller id full-duplex speakerphone handset record and playback handset on/off detection dsvd software upgradeable audio stereo audio 16-bit sd codec v.34 class modem analog front end full-duplex capture and playback operation at different sample rates internal 3d circuitphat?* stereo phase expander integrated opl3-compatible music synthesizer software and hardware volume control product overview the AD1821 modio? (modem over audio) soundcomm ? hsp (host signal processing) codec is a single-chip audio and communications subsystem for personal comp uters. the AD1821 solution includes the AD1821 mi xed-signal controller ic controller ic and modio? host signal processing soft- ware drivers. the AD1821 maintains full legacy compatibility with applications written for soundblaster pro and adlib, while servicing microsoft pc 97 application requirements. the AD1821 includes an internal opl3 compatible music synthe- sizer, phat? stereo circuitry for phase expanding the analog stereo output, an mpu-401 uart joystick interface with built-in timer, a dsp serial port and two i 2 s serial ports. the modio? drivers utilize cpu resources to implement high speed fax, data, voice (with echo cancellation) communications and maintain audio compatibility. the drivers enable simulta- neous execution of communications and audio with data flowing through the AD1821, and provide a graceful degradation of mo- dem performance as the host cpu load changes. the AD1821 on-chip plug and play routine provides configuration services for all integrated logical devices. features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 product overview . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 pin function descriptions . . . . . . . . . . . . . . . . . 10 host interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 serial interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 isa interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 AD1821 chip registers . . . . . . . . . . . . . . . . . . . . . . . . . . 20 AD1821 plug and play device configuration registers . . . 21 sound system direct registers . . . . . . . . . . . . . . . . . . . . 22 sound system indirect registers . . . . . . . . . . . . . . . . . . . 28 sb pro; adlib registers . . . . . . . . . . . . . . . . . . . . . . . . . 37 midi and mpu-401 registers . . . . . . . . . . . . . . . . . . . . . 38 game port register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 appendix a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 AD1821js and AD1821js-m . . . . . . . . . . . . . . . . . . . . 39 AD1821js plug and play internal rom . . . . . 39 AD1821js-m plug and play internal rom . . 40 appendix b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 plug and play key and alternate key sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 programming external eeproms . . . . . . . . . 42 reference designs and device drivers . . . 42 outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . 44 table of contents figures functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 figure 1. pio read cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 2. pio write cycle . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 3. dma read cycle . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 4. dma write cycle . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 5. codec transfers . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 6. dsp port timing . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 7. i 2 s serial port timing . . . . . . . . . . . . . . . . . . . . . . 7 figure 8. reset pulse width . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 9. serial interface right-justified mode . . . . . . . . . . 16 figure 10. serial interface i 2 s-justified mode . . . . . . . . . . . 16 figure 11. serial interface left-justified mode . . . . . . . . . . 16 figure 12. dsp serial interface (default frame rate) . . . . 19 figure 13. dsp serial interface (user programmed frame rate) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 14. dsp serial port . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 15. codec transfers . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 16. AD1821 frequency response plots . . . . . . . . . . 43 tables table i. dsp port time slot map . . . . . . . . . . . . . . . . . . . 17 table ii. chip register diagram . . . . . . . . . . . . . . . . . . . . . 20 table iii. logical devices and compatible plug and play device drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table iv. logical device configuration . . . . . . . . . . . . . . . 22 table v. sound system direct registers . . . . . . . . . . . . . . 22 table vi. codec transfers . . . . . . . . . . . . . . . . . . . . . . . . . 26 table vii. indirect register map and reset/default states . 29 table viii. sound system indirect registers . . . . . . . . . . . 30 table ix. soundblaster pro isa bus registers . . . . . . . . . . 37 table x. adlib isa bus registers . . . . . . . . . . . . . . . . . . . 38 table xi. midi isa bus registers . . . . . . . . . . . . . . . . . . . 38 table xii. game port isa bus registers . . . . . . . . . . . . . . 38
specifications standard test conditions unless otherwise noted temperature 25 c digital supply (v dd ) 5.0 v analog supply (v cc ) 5.0 v sample rate (f s ) 48 khz input signal frequency 1008 hz audio output passband 20 hz to 20 khz v ih 5.0 v v il 0v AD1821 rev. 0 C3C dac test conditions 0 db attenuation input full scale 16-bit linear mode 100 k w output load mute off measured at line output adc test conditions 0 db gain input C4 db relative to full scale line input selected 16-bit linear mode analog input parameter min typ max units full-scale input voltage (rms values assume sine wave input) phone_in, line, synth, cd, vid, mdm_in 1 v rms 2.83 v p-p mic with +20 db gain (mge = 1) 0.1 v rms 0.283 v p-p mic with 0 db gain (mge = 0) 1 v rms 2.83 v p-p input impedance* 17 k w input capacitance* 15 pf programmable gain amplifieradc parameter min typ max units step size (0 db to 22.5 db) (all steps tested) 1.5 db pga gain range span 22.5 db cd, line, microphone, modem, synthesizer, and video input analog gain/amplifiers, atte nuators/ mute parameter min typ max units cd, line, mic, synth, vid, mdm_in step size: (all steps tested) +12 db to C34.5 db 1.5 db input gain/attenuation range 46.5 db phone_in step size 0 db to C45 db: (all steps tested) 3.0 db input gain/attenuation range 45 db
AD1821 C4C rev. 0 digital decimation and interpolation filters* parameter min typ max units audio passband 0 0.4 f s hz audio passband ripple 0.09 db audio transition band 0.4 f s 0.6 f s hz audio stopband 0.6 f s hz audio stopband rejection 82 db audio group delay 12/f s sec group delay variation over passband 0.0 m s analog-to-digital converters parameter min typ max units resolution 16 bits signal-to-noise ratio (snr) (a-weighted, referenced to full scale) C82 C80 db total harmonic distortion (thd) (referenced to full scale) 0.011 0.015 % C79 C76.5 db audio dynamic range (C60 db input thd+n referenced to full-scale, a-weighted) 79 82 db audio thd+n (referenced to full-scale) 0.019 % C76 C74.5 db signal-to-intermodulation distortion* (ccif method) 82 db adc crosstalk* line inputs (input l, ground r, read r; input r, ground l, read l) C95 C80 db line to mic (input line, ground and select mic, read adc) C95 C80 db line to synth C95 C80 db line to cd C95 C80 db line to vid C95 C80 db gain error (full-scale span relative to nominal input voltage) 10 % interchannel gain mismatch (difference of gain errors) 1db adc offset error C22 +15 mv digital-to-analog converters parameter min typ max units resolution 16 bits signal-to-noise ratio (snr) (a-weighted) C83 C79 db total harmonic distortion (thd) 0.006 0.009 % C85 C80.5 db audio dynamic range (C60 db input thd+n referenced to full scale, a-weighted) 79 82 db audio thd+n (referenced to full scale) 0.013 0.017 % C78 C75.5 db signal-to-intermodulation distortion* (ccif method) 95 db gain error (full-scale span relative to nominal input voltage) 10 % interchannel gain mismatch (difference of gain errors) 0.5 db dac crosstalk* (input l, zero r, measure r_out; input r, zero l, measure l_out) C80 db total out-of-band energy (measured from 0.6 f s to 100 khz at l_out and r_out)* C45 db audible out-of-band energy (measured from 0.6 f s to 20 khz at l_out and r_out)* C75 db master volume attenuators (l_out and r_out, phone_out) parameter min typ max units master volume step size (0 db to C43.5 db) 1.5 db master volume step size (C43.5 db to C46.5 db) 1.5 db master volume output attenuation range span 46.5 db mute attenuation of 0 db fundamental* 80 db
rev. 0 C5C AD1821 digital mix attenuators* parameter min typ max units step size: i 2 s (0), i 2 s (1), music, isa 1.505 db digital mix attenuation range span 94.8 db analog output parameter min typ max units full-scale output voltage (at l_out, r_out, phone_out ) 2.8 v p-p output impedance* 570 w external load impedance* 10 k w output capacitance* 15 pf external load capacitance 100 pf v refx * 2.10 2.25 2.40 v v refx current drive* 100 m a v refx output impedance* 6.5 k w mute click (muted analog mixers), muted output minus unmuted output at 0 db 5mv system specifications* parameter min typ max units system frequency response ripple (line in to line out) 1.0 db differential nonlinearity 1 lsb phase linearity deviation 5 degrees static digital specifications parameter min typ max units high level input voltage (v ih )2v xtali 2.4 v low level input voltage (v il ) 0.8 v high level output voltage (v oh ), i oh = 8 ma? 2.4 v low level output voltage (v ol ), i ol = 8 ma 0.4 v input leakage current C10 +10 m a output leakage current C10 +10 m a power supply parameter min typ max units power supply rangeanalog 4.75 5.25 v power supply rangedigital 4.75 5.25 v power supply current 221 ma power dissipation 1105 mw analog supply current 51 ma digital supply current 170 ma analog power supply currentpower-down 2 ma digital power supply currentpower-down 24 ma analog power supply currentreset 0.2 ma digital power supply currentreset 10 ma power supply rejection (100 mv p-p signal @ 1 khz)* (at both analog and digital supply pins, both adcs and dacs) 40 db clock specifications* parameter min typ max units input clock frequency 33 mhz recommended clock duty cycle 25 50 75 % power-up initialization time 500 ms
AD1821 C6C rev. 0 timing parameters (guaranteed over operating temperature range) parameter symbol min typ max units iow / ior strobe width t stw 100 ns iow / ior rising to iow / ior falling t bwdn 80 ns write data setup to iow rising t wdsu 10 ns iow falling to valid read data t rddv 40 ns aen setup to iow / ior falling t aesu 10 ns aen hold from iow / ior rising t aehd 0ns adr setup to iow / ior falling t adsu 10 ns adr hold from iow / ior rising t adhd 0ns dack rising to iow / ior falling t dksu 20 ns data hold from ior rising t dhd1 2ns data hold from iow rising t dhd2 15 ns drq hold from iow / ior falling t drhd 25 ns dack hold from iow / ior rising t dkhd 10 ns data [sdi] input setup time to sclk* t s 15 ns data [sdi] input hold time from sclk* t h 10 ns frame sync [sdfs] hi pulse width* t fsw 80 ns c lock [sclk] to frame sync [sdfs] propagation delay *t pd 15 ns clock [sclk] to output data [sdo] valid* t dv 15 ns reset pulse width t rpwl 100 ns bclk hi pulse width t dbh 25 ns bclk lo pulse width t dbl 25 ns bclk period t dbp 50 ns lrclk setup t dls 5ns sdata setup t dds 5ns sdata hold t ddh 5ns notes *guaranteed, not tested. ?(all isa pins midi_out iol = 24 ma. refer to pin description for individual output drive levels. specifications subject to change without notice. t dksu t dkhd t aesu t aehd t stw t rddv t dhd1 t adsu t adhd drq (0, 1, 3) dack (0, 1, 3) aen pc_d [7:0] pc_a [15:0] ior figure 1. pio read cycle t dksu t dkhd t aesu t aehd t stw t dhd2 t adsu t adhd drq (0, 1, 3) dack (0, 1, 3) aen pc_d [7:0] pc_a [15:0] t wdsu iow figure 2. pio write cycle
AD1821 C7C rev. 0 t dkhd t dksu aen t drhd t aehd t aesu t stw t rddv t dhd1 drq (0, 1, 3) dack (0, 1, 3) pc_d [7:0] ior figure 3. dma read cycle t dkhd t dksu aen t drhd t aehd t aesu t stw t dhd2 drq (0, 1, 3) dack (0, 1, 3) pc_d [7:0] t wdsu iow figure 4. dma write cycle ior/iow data [7:0] t bwdn byte n n + 1 n + 2 n + 3 figure 5. codec transfers sclk t pd t fsw t s t h t dv sdfs sdi sdo bit 15 bit 14 bit 0 bit 15 bit 14 bit 0 figure 6. dsp port timing bclk sdata left-justified mode sdata right-justified mode i 2 s-justified mode sdata msb lsb t dbh t dbp t dbl t dls t dds t ddh t dds t ddh t dds t ddh t dds t ddh msb lrclk msb msb-1 figure 7. i 2 s serial port timing reset t rpwl figure 8. reset pulse width
AD1821 C8C rev. 0 environmental conditions ambient temperature rating: t amb = t case C (pd q ca ) t case = case temperature in c pd = power dissipation in w q ca = thermal resistance (case-to-ambient) q ja = thermal resistance (junction-to-ambient) q jc = thermal resistance (junction-to-case) package u ja u jc u ca pqfp 77 c/w 7 c/w 70 c/w absolute maximum ratings* parameter min max units power supplies digital (v dd ) C0.3 6.0 v analog (v cc ) C0.3 6.0 v input current (except supply pins) 10.0 ma analog input voltage (signal pins) C0.3 v cc + 0.3 v digital input voltage (signal pins) C0.3 v dd + 0.3 v ambient temperature (operating) 0 +70 c storage temperature C65 +150 c *stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. ordering guide temperature package function package model range description description option* AD1821js 0 c to +70 c 100-lead pqfp audio/modem s-100 AD1821js-m 0 c to +70 c 100-lead pqfp modem s-100 *s = plastic quad flatpack. caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the AD1821 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. the AD1821 latchup immunity has been demonstrated at 3 +100 ma/C80 ma on all pins when tested to industry standard/jedec methods. warning! esd sensitive device
AD1821 C9C rev. 0 pin configuration 100-lead pqfp (s-100) 5 4 3 2 7 6 9 8 1 11 10 16 15 14 13 18 17 20 19 22 21 12 24 23 26 25 28 27 30 29 32 33 34 35 36 38 39 40 41 42 43 44 45 46 47 48 49 50 31 37 76 77 78 79 74 75 72 73 70 71 80 65 66 67 68 63 64 61 62 59 60 69 57 58 55 56 53 54 51 52 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 pin 1 identifier top view (not to scale) sport_sdfs/ld_drq/vol_up gnd v dd pc_d (0) gnd v dd gnd pc_d (1) pc_d (2) pc_d (3) pc_d (4) pc_d (5) pc_d (6) pc_d (7) r_vid l_vid v cc gnda v ref v ref_x r_filt l_filt r_aafilt l_aafilt r_line l_line mdm_in/phone_in mic r_synth l_synth r_cd l_cd a_2 a_1 irq (5) irq (7) irq (9)/irq (14) irq (10)/irq (4) irq (11)/irq (9)/irq (4) irq (15)/irq (11) drq (0) drq (1) drq (3) v dd gnd xctl1/ring/ld_sel1 xctl0/pclko/pnprst midi _out midi_in gnd xtalo xtali v dd dack (0) dack (1) dack (3) ee_clk ee_data b_x b_y a_x a_y b_1 b_2 i 2 s0_data/vol_up i 2 s0_lrclk/vol_dn phone_out mdm_out/r_out l_out AD1821 i 2 s0_bclk/gnd pc_a (15) pc_a (14) pc_a (13) pc_a (12) pc_a (11) pc_a (10) pc_a (9) pc_a (8) pc_a (7) pc_a (6) pc_a (5) pc_a (4) pc_a (3) pc_a (2) pc_a (1) pc_a (0) aen ior v dd gnd reset rx3d cx3d iow nc = no connect i 2 s1_lrclk/mdm_sel/irq (12)/irq (13) i 2 s1_data/irq (3)/irq (9) i 2 s1_bclk/mdm_irq sport_sdi/ld_irq/vol_dn/gnd sport_sdo/ld_dack/vol_dn/gnd sport_sclk/ld_sel/nc
AD1821 C10C rev. 0 pin function descriptions analog signals pin name pqfp i/o description mic 44 i microphone input. the mic input may be either line-level or C20 db from line-level (the difference being made up through a software controlled 20 db gain block). the mono mic input may be sent to the left and right channel of the adc for conversion, or gained/ attenuated from +12 db to C34.5 db in 1.5 db steps and then summed with left and right line out before the master volume stage. l_line 42 i left line-level input. the left line-level input may be: sent to the left channel of the adc; gained/attenuated from +12 db to C34.5 db in 1.5 db steps and then summed with left line out. r_line 41 i right line-level input. the right line-level input may be: sent to the right channel of the adc; gained/attenuated from +12 db to C34.5 db in 1.5 db steps and then summed with right line out. l_synth 46 i left synthesizer input. the left midi upgrade line-level input may be: sent to the left channel of the adc; gained/attenuated from +12 db to C34.5 db in 1.5 db steps and then summed with left line out. r_synth 45 i right synthesizer input. the right midi upgrade line-level input may be: sent to the right channel of the adc; gained/attenuated from +12 db to C34.5 db in 1.5 db steps and then summed with right line out. l_cd 48 i left cd line-level input. the left cd line-level input may be: sent to the left channel of the adc; gained/attenuated from +12 db to C34.5 db in 1.5 db steps and then summed with left line out. r_cd 47 i right cd line-level input. the right cd line-level input may be: sent to the right chan- nel of the adc; gained/attenuated from +12 db to C34.5 db in 1.5 db steps and then summed with right line out. l_vid 32 i left video input. the left audio track for a video line-level input may be: sent to the left channel of the adc; gained/attenuated from +12 db to C34.5 db in 1.5 db steps and then summed with left line out. r_vid 31 i right video input. the right audio track for a video line-level input may be: sent to the right channel of the adc; gained/attenuated from +12 db to C34.5 db in 1.5 db steps and then summed with right line out. l_out 30 o left output. left channel line-level post-mixed output. the final stage passes through the master volume block and may be attenuated 0 db to C45 db in 1.5 db steps. mdm_out/ 29 o modem output/right output. right channel line-level post-mixed output. the final stage r_out pas ses through the master volume block and may be attenuated 0 db to C45 db in 1.5 db steps. mdm_in/ 43 i modem input/phone input. line-level input from a daa/modem chipset. phone_in phone_out 28 o phone output. line-level output from a daa/modem chipset. rx3d 26 o phat?* stereo phase expander filter network, resistor pin. cx3d 27 i phat?* stereo phase expander filter network, capacitor pin.
AD1821 C11C rev. 0 parallel interface (all outputs are 24 ma drivers) pin name pqfp i/o description pc_d[7:0] 85C88, 91C94 83C86, 89C92 i/o bidirectional isa bus pc data, 24 ma drive. connects the AD1821 to the low byte data on the bus. irq(x)* 75C81, 83 o host interrupt request, 24 ma drive. irq (3)/irq (9), irq(5), irq(7), irq(9)/irq (14), irq(10)/irq(4), irq(11)/irq (9)/irq (4), irq(12)/ irq(13), irq(15)/irq (11). active hi signals indicating a pending interrupt. drq(x) 72C74 o dma request, 24 ma drive. drq(0), drq(1), drq(3). active hi signals indicating a request for dma bus operation. pc_a[15:0] 4C19 i isa bus pc address. connects the AD1821 to the isa bus address lines. aen 20 i address enable. low signal indicates a pio transfer. dack (x) 59C61 i dma acknowledge. dack(0), dack(1), dack(3). active lo signal indicating that a dma operation can begin. ior 22 i i/o read. active lo signal indicates a read operation. iow 21 i i/o write. active hi signal indicates a write operation. reset 25 i reset. active hi. game port pin name pqfp i/o description a_1 50 i game port a, button #1. a_2 49 i game port a, button #2. a_x 54 i game port a, x-axis. a_y 53 i game port a, y-axis. b_1 52 i game port b, button #1. b_2 51 i game port b, button #2. b_x 56 i game port b, x-axis. b_y 55 i game port b, y-axis. midi interface signal (24 ma drivers) pin name pqfp i/o description midi_in 66 i rxd midi input. this pin is typically connected to pin 15 of the game port connector. midi_out 67 o txd midi output. this pin is typically connected to pin 12 of the game port connector.
AD1821 C12C rev. 0 muxed serial ports ( 8 ma drivers) pin name pqfp i/o description i 2 s(0)_bclk* 3 i i 2 s (0) bit clock. i 2 s(0)_lrclk* 2 i i 2 s (0) left/right clock. i 2 s(0)_data* 1 i i 2 s (0) serial data input. i 2 s(1)_bclk* 82 i i 2 s (1) bit clock. i 2 s(1)_lrclk* 83 i i 2 s (1) left/right clock. i 2 s(1)_data* 81 i i 2 s (1) serial data input. sport_sdi* 100 i serial port digital serial input. sport_sclk* 97 o serial port serial clock. sport_sdfs* 98 o serial port serial data frame synchronization. sport_sdo* 99 o serial port serial data output. miscellaneous analog pins pin name pqfp i/o description v ref_x 36 o voltage reference. nominal 2.25 volt reference available for dc-cou- pling and level-shifting. v ref_x should not be used to sink or source sig- nal current. v ref 35 i voltage reference filter. voltage reference filter point for external by- passing only. l_filt 38 i left channel filter. requires a 1.0 m f to analog ground for proper operation. r_filt 37 i right channel filter. requires a 1.0 m f to analog ground for proper operation. l_aafilt 40 i left channel antialias filter. this pin requires a 270 pf npo capacitor to analog ground for proper operation. r_aafilt 39 i right channel antialias filter. this pin requires a 270 pf npo capacitor to analog ground for proper operation. crystal pin pin name pqfp i/o description xtalo 64 o 33 mhz crystal output. if no crystal is present leave xtalo unconnected. xtali 63 i 33 mhz clock. when using a crystal as a clock source, the crystal should be connected between the xtali and xtalo pins. clock in- put may be driven into xtali in place of a crystal. when using an ex- ternal clock, v ih must be 2.4 v rather than the v ih of 2.0 v specified for all other digital inputs. external logical devices pin name pqfp i/o description ld_irq* 100 i logical device irq. ld_dack* 99 o logical device dack. ld_drq* 98 i logical device drq. ld_sel * 97 o logical device select. mdm_sel * 83 o modem chip set select. mdm_irq * 82 i modem chip set irq. ld_sel1 * 69 o logical device (1) select. pnprst* 68 o plug and play reset.
AD1821 C13C rev. 0 hardware volume pins pin name pqfp i/o description vol_dn * 2, 99, 100 i master volume down. modifies output level on pins l_out and r_out. contains a 10 k w internal pull-up resistor. when asserted lo, decreases master volume by 1.5 db/sec. must be asserted at least 25 ms to be recognized. when asserted simultaneously with vol_up, output is muted. output level modifica- tion reflected in indirect register 0 29. vol_up* 1, 98 i master volume up. modifies output level on pins l_out and r_out. con- tains a 10 k w internal pull-up resistor. when asserted lo, increases master volume by 1.5 db/sec. must be asserted at least 25 ms to be recognized. when asserted simultaneously with vol_up, output is muted. output level modifica- tion reflected in indirect register 0 29. control pins pin name pqfp i/o description xctl0* 68 o external control 0. the state of this pin (ttl hi or lo) is reflected in codec indexed register. this pin is an open drain driver. pclko* 68 o programmable clock output. this pin can be programmed to generate an out- put clock equal to f s , 8 f s , 16 f s , 32 f s , 64 f s , 128 f s or 256 f s . mpeg decoders typically require a master clock of 256 f s for a udio synchronization. xctl1* 69 o external control 1. the state of this pin (ttl hi or lo) is reflected in codec indexed register. open drain, 8 ma active 0.5 ma pull-up resistor. ring* 69 i ring indicator. used to accept the ring indicator flag from the daa. power supplies pin name pqfp i/o description v cc 33 i analog supply voltage (+5 v). gnda 34 i analog ground. v dd 23, 62, 71, i digital supply voltage (+5 v). 89, 95 gnd 3*, 24, 65, i digital ground. 70, 84, 90, 96, 99*, 100* optional eeprom pins pin name pqfp i/o description ee_clk 58 o eeprom clock. ee_data 57 i eeprom data. *the position of this pin location/function is dependent on the eeprom data.
AD1821 C14C rev. 0 host interface the AD1821 contains all necessary isa bus interface logic on- chip. this logic includes address decoding for all onboard resources, control and signal interpretation, dma selection and control logic, irq selection and control logic, and all interface configuration logic. the AD1821 supports a type f dma request/grant architec- ture for transferring data with the isa bus through the 8-bit interface. the AD1821 also supports dack preemption. pro- grammed i/o (pio) mode is also supported for control register accesses and for applications lacking dma control. the AD1821 includes dual dma count registers for full-duplex operation enabling simultaneous capture and playback on sepa- rate dma channels. codec functional description the AD1821s full-duplex stereo codec supports business a udio and multimedia applications. the codec includes stereo audio convert ers, complete on-chip filtering, mpc level-2 and level-3 compliant analog mixing, programmable gain and at- tenuation, a variable sample rate converter, extensive digital mixing and fifos buffering the plug and play isa bus interface. when using modio modem software, phone_in and r_out channels are used to support modem and telephony features. analog inputs the codec contains a stereo pair of ?d analog-to-digital con- verters (adc). inputs to the adc can be selected from the fol- lowing analog signals: mono (phone_in), mono microphone (mic), stereo line (line), external stereo synthesizer (synth), stereo cd rom (cd), stereo audio from a video source (vid) and post-mixed stereo or mono line output (out). analog mixing phone_in, mic, line, synth, cd and vid can be mixed in the analog domain with the stereo line out from the sd digital-to-analog converters (dac). each channel of the stereo analog inputs can be independently gained or attenuated from +12 db to C34.5 db in 1.5 db steps, except for phone_in, which has a range of 0 db to C45 db steps. the summing path for the mono inputs (mic, and phone_in to line out) du- plicates mono channel data on both the left and right line out, which can also be gained or attenuated from +12 db to C34.5 db in 1.5 db steps for mic, and +0 db to C45.5 db in 3 db steps for phone_in. the left and right mono summing signals are always identical being equally gained or attenuated. analog-to-digital datapath the selector sends left and right channel information to the pro- grammable gain amplifier (pga). the pga following the selec- tor allows independent gain for each channel entering the adc from 0 db to 22.5 db in 1.5 db steps. for supporting time correlated i/o echo cancellation, the adc is capable of sampling microphone data on the left channel and the mono summation of left and right out on the right channel. the codec can operate in either a global stereo mode or a glo- bal mono mode with left channel inputs appearing at both chan- nels of the 16-bit sd converters. data can be sampled at the programmed sampling frequency (from 4 khz to 55.2 khz with 1 hz resolution). digital mixing & sample rates the audio adc sample rate and the audio dac sample rates are completely independent. the AD1821 includes a variable sample rate converter that lets the codec instantaneously change and process sample rates from 4 khz to 55.2 khz with a resolution of 1 hz. the in-band integrated noise and distor- tion artifacts introduced by rate conversions are below C90 db. up to four channels of digital data can be summed together and presented to the stereo dac for conversion. each digital chan- nel pair can contain information encoded at a different sample rate. for example, 8 khz .wav data received from the isa inter- face, 48 khz mpeg audio data received from i 2 s(0), digital 44.1 khz cd data received from i 2 s(1) and internally generated 22.05 khz music data may be summed together and converted by the dacs. digital-to-analog datapath the internally generated music synthesizer data, pcm data received from the isa interface, data received from the i 2 s(0) port and data received from the i 2 s(1) port, and the dsp serial port passes through an attenuation mute stage. the attenuator allows independent control over each digital channel, which can be attenuated from 0 db to C94.5 db in 1.5 db steps before be- ing summed together and passed to the dac, or the channel may be muted entirely. analog outputs the analog output of the dac can be summed with any of the analog input signals. the summed analog signal enters the master volume stage where each channel l_out, r_out and phone_out may be attenuated from 0 db to C46.5 db in 1.5 db steps or muted. digital data types the codec can process 16-bit twos-complement pcm linear digital data, 8-bit unsigned magnitude pcm linear data and 8-bit m -law or a-law companded digital data as specified in the control registers. the AD1821 also supports adpcm encoded in the creative soundblaster adpcm formats. host-based echo cancellation support the AD1821 supports time correlated i/o data format by pre- senting mic data on the left channel of the adc and the mono summation of left and right out on the right channel. the adc sample rates are independent of the dac sample rate allow- ing the AD1821 to support adc time correlated i/o data at 8 khz and dac data at any other sample rate in the range of 4 khz to 55.2 khz simultaneously. telephony support the AD1821 contains a phone_in input and a phone_out output. these pins are supplied so the AD1821 may be connected to a modem chip set, a telephone handset or down-line phone. wss and soundblaster compatibility windows sound system software audio compatibility is built into the AD1821. soundblaster emulation is provided through the soundblaster register set and the internal music synthesizer. soundblaster pro version 2.01 functions are supported, including record and cre- ative soundblaster adpcm. virtually all applications developed for soundblaster, windows sound system, adlib and midi mpu-401 platforms run on the AD1821 soundcomm ? controller. follow the same development process for the controller as you would for these other devices.
AD1821 C15C rev. 0 as the AD1821 contains soundblaster (compatible) and windows sound system logical devices. you may find the following related development kits useful when developing AD1821 applications. developer kit for soundblaster series , 2nd ed. ? 1993, creative labs, inc., 1901 mccarthy blvd., milpitas, ca 95035 microsoft windows sound system driver development kit ( cd ), version 2.0, ? 1993, microsoft corp., one microsoft way, redmond, wa 98052 the following reference texts can serve as additional sources of information on developing applications that run on the AD1821. s. de furia & j. scacciaferro, the midi implementation book , (? 1986, third earth, pompton lake) c. petzold, programming windows: the microsoft guide to writ- ing applications for windows 3.1 , 3rd. ed., (? 1992, microsoft press, redmond) k. pohlmann, principles of digital audio , (? 1989, sams, indianapolis) a. stolz, the soundblaster book , (? 1993, abacaus, grand rapids) j. strawn, digital audio engineering , an anthology , (? 1985, kaufmann, los altos) yamamoto, midi guidebook , 4th. ed., (? 1987, 1989, roland corp.) multimedia pc capabilities the AD1821 is mpc-2 and mpc-3 compliant. this compli- ance is achieved through the AD1821s flexible mixer and the embedded chip resources. music synthesis the AD1821 includes an embedded music synthesizer that emulates industry standard opl3 fm synthesizer chips and delivers 20 voice polyphony. the internal synthesizer generates digital music data at 22.05 khz and is summed into the dacs digital data stream prior to conversion. to sum synthesizer data with the adc output, the adc must be programmed for a 22.05 khz sample rate. the synthesizer is a hardware implementation of eusynth-1+ code that was developed by euphonics, a research and devel- opment company that specializes in audio processing and electronic music synthesis. wavetable midi inputs the AD1821 has a dedicated analog input for receiving an ana- log wavetable synthesizer output. alternatively, a wavetable synthesizers i 2 s formatted digital output can be directly con- nected to one of the AD1821s i 2 s serial ports. digital wave- table data from the AD1821s i 2 s port may be summed with other digital data streams being handled by the AD1821 and then sent to the 16-bit sd dac. midi the primary interface for communicating midi data to and from the host pc is the compatible mpu-401 interface that operates in uart mode. the mpu-401 interface has two built-in fifos: a 64 byte receive fifo and a 16 byte transmit fifo. game port an ibm-compatible game port interface is provided on chip. the game port supports up to two joysticks via a 15-pin d-sub connector. joystick registers supporting the microsoft direct input standard are included as part of the register map. the AD1821 may be programmed to automatically sample the game port and save the value in the joystick position data reg- ister. when enabled, this feature saves up to 10% cpu mips by off-loading the host from constantly polling the joystick port. volume control the registers that control the master volume output stage are accessible through the parallel port. master volume output can also be controlled through a 2-pin hardware interface. one pin is used to increase the gain, the other pin attenuates the output and both pins together entirely mute the output. once muted, any further activity of these pins will unmute the AD1821s output. plug and play configuration the AD1821 is fully plug and play configurable. for mother- board applications, the built-in plug and play protocol can be disabled with a software key providing a back door for the bios to configure the AD1821s logical devices. for information on the plug and play mode configuration process, see the plug and play isa specification version 1.0a (may 5, 1994) . all the AD1821s logical devices comply with plug and play resource definitions described in the specification. the AD1821 may alternatively be configured using an op tional plug and play resource rom. when the eeprom is present, some additional AD1821 muxed-pin features become available. for example, pins that control an external modem logical device are muxed with the dsp serial port. some of these pin option combinations are mutually exclusive (see appendix a for more information). references the AD1821 also complies with the following related specifica- tions; they can be used as an additional reference to AD1821 op- erations beyond the material in this data sheet. plug and play isa specification, version 1.0a , ? 1993, 1994, intel corp. & microsoft corp., one microsoft way, redmond, wa 98052 multimedia pc level 2 specification , ? 1993, multimedia pc marketing council, 1730 m st. nw, suite 707, washington, dc 20036 midi 1.0 detailed specification & standard midi files 1.0, ? 1994, midi manufacturers association, po box 3173 la habra, ca 90632-3173 recommendation g.711-pulse code modulation (pcm) of voice frequencies ( m -law & a-law companding), the international telegraph and telephone consultative committee ix plenary assembly blue book, volume iii - fascicle iii.4, general aspects of digital transmission systems; terminal equipments, recommendations g.700 - g.795, (geneva, 1988), isbn 92-61-03341-5 ima digital audio doc-pac (ima-adpcm), ? 1992, inter- active multimedia association, 48 maryland avenue, suite 202, annapolis, md 21401-8011 eusynth-1+
AD1821 C16C rev. 0 serial interfaces i 2 s serial ports the two i 2 s serial ports on the AD1821 accept serial data in the following formats: ri ght-justified, i 2 s-justified and left-justified. figure 9 shows the right-justified mode. lrclk is hi for the left channel and lo for the right channel. data is valid on the rising edge of the bclk. the msb is delayed 16-bit clock periods from an lrclk transition, so that when there are 64 bclk periods per lrclk period, the lsb of the data will be right-justified to the next lrclk transition. lrclk bclk sdata 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 left channel right channel 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 figure 9. serial interface right-justified mode figure 10 shows the i 2 s-justified mode. lrclk is lo for the left channel and hi for the right channel. data is valid on the rising edge of bclk. the msb is left-justified to an lrclk transition, but with a single bclk period delay. lrclk bclk sdata 1514131211109876543210 left channel right channel 14131211109876543210 15 figure 10. serial interface i 2 s-justified mode figure 11 shows the left-justified mode. lrclk is hi for the left channel and lo for the right channel. data is valid on the rising edge of bclk. the msb is left-justified to an lrclk transition, with no msb delay. lrclk bclk sdata 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 left channel right channel 14131211109876543210 15 figure 11. serial interface left-justified mode bidirectional dsp serial interface the AD1821 soundcomm ? controller transmits and receives both data and control/status information through its dsp serial inter- face port (sport). the AD1821 is always the bus master and supplies the frame sync and the serial clock. the AD1821 has four pins assigned to the sport: sdi, sdo, sdfs, and sclk. the sport has two operating modes: monitor and intercept. the sport always monitors the various data streams being processed by the AD1821. in intercept mode, any of the digital data stream s can be manipulated by the dsp before reaching the final adc or dac stages. the sdi and sdo pins handle the serial data input and output of the AD1821. communication in and out of the AD1821 requires that bits of data be transmitted after a rising edge of sclk and sampled on the falling edge of sclk. the sclk frequency is always 11 mhz (or 1/3 or xtali). dsp serial port interface time slots are mapped as shown in table i.
AD1821 C17C rev. 0 table i. dsp port time slot map time slot sdi pin sdo pin 0 control word input status word output 1 control register data input control register data output 2 * ss/sb adc right input (to isa) ss/sb adc right output (from codec) 3 * ss/sb adc left input (to isa) ss/sb adc left output (from codec) 4 * ss/sb dac right input (to codec) ss/sb dac right output (from isa) 5 * ss/sb dac left input (to codec) ss/sb dac left output (from isa) 6 * fm dac right input (to codec) fm dac right output (from fm synth block) 7 * fm dac left input (to codec) fm dac left output (from fm synth block) 8* i 2 s (1) dac right input (to codec) i 2 s (1) dac right output (from i 2 s port [1]) 9* i 2 s (1) dac left input (to codec) i 2 s (1) dac left output (from i 2 s port [1]) 10 * i 2 s (0) dac right input (to codec) i 2 s (0) dac right output (from i 2 s port [0]) 11 * i 2 s (0) dac left input (to codec) i 2 s (0) dac left output (from i 2 s port [0]) *this data is ignored by the AD1821 unless the channel pair is in intercept mode (see below). ss = sound system mode sb = soundblaster mode at start-up (after pin reset), there are exactly 12 time slots per frame. the frame rate will be 57,291 and 2/3 hz (11 mhz sclk/ (16 bits 12 slots)). interfacing with an analog devices 21xx family dsp can be achieved by putting the adsp-21xx in 24 slot per frame mode, where the first 12 and second 12 slots in the adsp-21xx frame are identical. the frame rate can be changed from its default by a write to the dfs(2:0) bits in register 33. rate choices are: maximum (57,29 1 and 2/3 hz default), ss capture rate, ss playback rate, fm rate, i 2 s port (1) rate, or i 2 s port (0) rate. when the frame rate is less than 57,261 and 2/3 hz, extra sclk periods are added to fill up the time. the number of sclk periods added will vary somewhat from frame to frame. to control the sample data flow of each channel through the dsp port, valid input, valid output and request bits are located in the control and status words. if the specified channel sample rate is equal to the frame rate, these bits may be ignored since they will always be set to 1. by default, the dsp serial port allows only codec sample data i/o to be monitored. intercept modes must be enabled to make subs ti- tutions in sample data flow to and from the codec. there are five bits in ss register 33, which enable intercept mode for ss ca pture, ss playback, fm playback, i 2 s port (1) playback and i 2 s port (0) playback. control word input (slot 0 sdi) 15 14 13 12 11 10 9 8 fclr res res sscvi sspvi fmvi is1vi is0vi 76543210 alive r/w ia[5:0] ia [5:0] indirect register address. sound system indirect register address defines the address of indirect registers shown in table vi. r/w read/write request. either a read from or a write to an ss indirect register occurs every frame. setting this bit ini- tiates an ss indirect register read while clearing this bit initiates an ss indirect register write. alive dsp port alive bit. when set, this bit indicates to the power-down timer that the dsp port is active. when cleared, this bit indicates that the dsp port is inactive. is0vi i 2 s port 0 substitution data input valid flag. this bit is ignored if: (1) intercept mode is not enabled for the i 2 s port 0 channel pair, or (2) the AD1821 did not request data from the i 2 s port 0 channel pair in the previous frame. otherwise, setting this bit indicates that slots 10 and 11 contain valid right and left i 2 s port 0 substitution data. when this bit is cleared, data in slots 10 and 11 is ignored. is1vi i 2 s port 1 substitution data input valid flag. this bit is ignored if: (1) intercept mode is not enabled for i 2 s port 1 channel pair or (2) the AD1821 did not request data from the i 2 s port channel pair in the previous frame. oth- erwise, setting this bit indicates that slots 8 and 9 contain valid right and left i 2 s port 1 substitution data. when this bit is cleared, data in slots 8 and 9 is ignored. fmvi fm synthesis substitution data input valid flag. this bit is ignored if: (1) intercept mode is not enabled for the fm synthesis channel pair or (2) the AD1821 did not request data from the fm synthesis channel pair in the pre- vious frame (see the fmrq bit 9 in the status word output). otherwise, setting this bit to 1 indicates that slots 6 and 7 contain valid right and left fm synthesis channel substitution data. when this bit is reset to 0, data in slots 6 and 7 is ignored.
AD1821 C18C rev. 0 sspvi ss/sb playback substitution data input valid flag. this bit is ignored if: (1) intercept mode is not enabled for ss/sb playback or (2) the AD1821 did not request data for ss/sb playback in the previous frame (see the ssprq bit in the status word output). otherwise, setting this bit indicates that slots 4 and 5 contain valid right and left ss/sb playback substitution data. if in capture rate equal to playback rate mode, setting this bit also in- dicates that valid capture substitution data is being sent to the AD1821. if not in modem mode, right and left channel capture substitution data is accepted in slots 2 and 3 respectively. if in modem mode, only mono capture substitution data is accepted in slots 2 and 3. when this bit is cleared, data in all slots controlled by this bit, as de- fined above, is ignored. sscvi ss/sb capture substitution data input valid flag. this bit is ignored if: (1) intercept mode is not enabled for ss/ sb capture or (2) the AD1821 did not request data for ss/sb capture in the previous frame (see the sscrq bit in the status word output). otherwise, setting this bit indicates that valid ss/sb capture substitution data is being sent to the AD1821. if not in modem mode, or dsp port or isa bus based, right and left channel capture data is accepted in slots 2 and 3 respectively. if in modem mode, only mono capture substitution data is accepted in slot 3, because slot 2, which is mapped to the right capture channel, is being used for modem. this mono data will, however, be sent to both left and right isa ss/sb capture channels. when this bit is cleared, data in slots 3 and 2 is ignored. res reserved: to ensure future compatibility write 0 to all reserved bits. fclr dsp port clear status flag. when this bit is set, (write 1), the pnpr and pdn flag bits in the status word (bits 15 and 14 of slots 0 sdo) are cleared. when this bit is cleared, (writing a 0), it has no effect on pnpr and pdn and preserves them in the previous states. status word output (slot 0 sdo) 15 14 13 12 11 10 9 8 pdn pnpr res sscvo sspvo fmvo is1vo is0vo 76543210 mb1 mb0 res sscrq ssprq fmrq is1rq is0rq is0rq i 2 s port (0) input request flag. this bit is set if intercept mode is enabled for i 2 s port (0) and its four-word stereo input buffer is not full. is1rq i 2 s port (1) input request flag. this bit is set if intercept mode is enabled for i 2 s port (1) and its four-word stereo input buffer is not full. fmrq fm synthesis input request flag. this bit is set if intercept mode is enabled for fm synthesis and its four-word stereo input buffer is not full. ssprq ss/sb capture input request flag. this bit is set if intercept mode is enabled for ss/sb playback and its four- word stereo input buffer is not full. sscrq ss/sb capture input request flag. this bit is set if intercept mode is enabled for ss/sb capture and its four-word stereo input buffer is not full. mb0 mailbox 0 status flag. this bit is set if the most recent action to ss indirect register 42 (dsp port mail box 1) was a write, and is cleared if the most recent action was a read. the status of this bit is also reflected in ss indirect register 33. it may be used as a handshake bit to facilitate communication between a dsp on the dsp port and a host cpu on the isa bus. mb1 mailbox 1 status flag. this bit is set if the most recent action to ss indirect register 43 (dsp port mail box 1) was a write and is cleared if the most recent action was a read. the status of this bit is also reflected in ss indirect register 33. it may be used as a handshake bit to facilitate communication between a dsp on the dsp port and a host cpu on the isa bus. is0vo i 2 s port 0 valid out. this bit is set if slots 10 and 11 contain valid right and left i 2 s port 0 data. is1v1 i 2 s port 1 valid out. this bit is set if slots 8 and 9 contain valid right and left i 2 s port 1 data. fmvo fm synthesis valid out. this bit is set if slots 6 and 7 contain valid left and right fm synthesis data. sspvo ss/sb playback valid out. this bit is set if slots 4 and 5 contain valid right and left ss/sb playback data. sscvo ss/sb capture valid out. this bit is set if valid ss/sb capture data is being transmitted. if not in a modem mode, slots 2 and 3 will contain valid right and left ss/sb capture data. if in modem mode, only slot 3 will contain valid left ss/sb capture data as slot 2 and the adc right channel are used by the modem.
AD1821 C19C rev. 0 pnpr plug and play reset flag. this bit is set by an AD1821 reset (resetb pin asserted low) or by a plug and play reset command. this bit is cleared by the assertion of the fclr bit in the control word. while this bit is set, all attempts to write an ss indirect register via the dsp port will be ignored and fail. this is to ensure that plug and play resets are immediately applied to the application running on the dsp, without requiring them to continuously poll the plug and play reset status bit. during the frame in which this bit is cleared (by asserting fclr), an attempt to write an ss indirect register will succeed. if the fclr bit is continuously asserted, writes to indirect registers via the dsp port will always be enabled. a plug and play reset command will set this pnpr bit high during at least one frame. pdn power-down flag. this bit is set by an AD1821 reset (resetb pin asserted low), or by an AD1821 power- down. before an AD1821 power-down sequence shuts down the dsp port, at least one frame will be sent with this bit set. this bit can be cleared by the assertion of the fclr (dsp port status clear) bit in the control word, pro- viding the AD1821 is no longer in power-down. the sdfs pin is used for the serial interface frame synchronization. new frames are marked by a one sclk duration hi pulse, driven out on sdfs, one serial clock period before the frame begins. upon initializing, there are exactly 12 time slots per fra me and 16 bits per time slot. the frame rate is 57,291 and 2/3 hz (11 mhz sclk /(16 bits 12 slots). the frame rate can also be changed from the default value by reprogramming the rate in registers. the frame rate can run at the default rate or be programmed to m atch the modem sample rate, adc capture rate, dac playback rate, music sample rate, i 2 s(1) sample rate or i 2 s(0) sample rate. when the frame rate is not equivalent to the sample rate, valid out, request in and valid in bits are used to control the sample dat a flow. when the frame rate is equivalent to the sample rate, valid and request bits can be ignored. sclk sdi or sdo sdfs 15 14 13 0 1 2 3 15 14 13 0 1 2 3 151413 0 1 2 3 sample period n slot 0 slot 15 slot 0 slot 15 slot 0 slot 15 sample period n + 1 sample period n + 2 figure 12. dsp serial interface (default frame rate) sclk sdi or sdo sdfs 15 14 13 0 1 2 3 15 14 13 0 1 2 3 15 14 13 0 1 2 3 sample period n slot 0 slot 15 slot 0 slot 15 slot 0 slot 15 sample period n + 1 sample period n + 2 figure 13. dsp serial interface (user programmed frame rate)
AD1821 C20C rev. 0 figure 14 illustrates the flexibility of the dsp serial port interface. this port can monitor or intercept any of the digital s treams man- aged by the AD1821. any adc or dac data stream can be intercepted by the port, shipped to an external dsp or asic manipu- lated, and returned to any dac summing path or to the adc. plug and play isa bus parallel interface audio dac pga audio/ modem adc serial port interface music synthesizer format fifo i 2 s serial port (0) a m selector a m a m a m i 2 s serial port (1) format fifo figure 14. dsp serial port isa interface AD1821 chip registers table ii, chip register diagram, details the AD1821 direct register set available from the isa bus. prior to any accesses by th e host, the pc i/o addressable ports must be configured using the plug and play resources. table ii. chip register diagram register type-register name register pc i/o address plug and play address 0x279 write_data 0xa79 read_data relocatable in range 0x203 C 0x3ff sound system codec codec registers 0x(ss base+0 C ss base+15) relocatable in range 0x100 C 0x3ff see table v soundblaster pro music0: address (w), status (r) 0x(sb base) relocatable in range 0x010 C 0x3f0 music0: data (w) 0x(sb base+1) music1: address (w) 0x(sb base+2) music1: data (w) 0x(sb base+3) mixer address (w) 0x(sb base+4) mixer data (w) 0x(sb base+5) reset (w) 0x(sb base+6 or 7) music0: address (w) 0x(sb base+8) music0: data (w) 0x(sb base+9) input data (r) 0x(sb base+a or +b) status (r), output data (w) 0x(sb base+c or +d) status (r) 0x(sb base+e or +f)
AD1821 C21C rev. 0 register type-register name register pc i/o address adlib music0: address (w), status (r) 0x(adlib base) relocatable in range 0x100 C 0x3f8 music0: data (w) 0x(adlib base+1) music1: address (w) 0x(adlib base+2) music1: data (w) 0x(adlib base+3) midi mpu-401 midi data (r/w) 0x(midi base) relocatable in range 0x100 C 0x3f8 midi status (r), command (w) 0x(midi base+1) game port game port i/o 0x(game base +0 to game base +7) relocatable in range 0x100 C 0x3f8 AD1821 plug and play device configuration registers the AD1821 may be configured according to the intel/microsoft plug and play specification using the internal rom. alternativel y, the pnp configuration sequence may be bypassed using the alternate key sequence described in appendix a. the operating system configures/reconfigures AD1821 plug and play logical devices after system boot. there are no boot-devices among the plug and play logical devices in the AD1821. non-plug and play bios systems configure the AD1821s logical devices after boot using drivers. depending on bios implementations, plug and play bios systems may configure the AD1821s logical devices before post or after boot. see the plug and play isa specification version 1.0a for more information on configura- tion control. to complete this configuration, the system reads resource data from the AD1821s on-chip resource rom and from any other plug and play cards in the system, and then arbitrates the configuration of system resources with a heuristic algorit hm. the algorithm maximizes the number of active devices and the acceptability of their configurations. the system considers all plug and play logical device resource data at the same time and makes a conflict-free assignment of re - sources to the devices. if the system cannot assign a conflict-free resource to a device, the system does not configure or acti vate the device. all configured devices are activated. the systems plug and play support selects all necessary drivers, starts them and maintains a list of system resources allocate d to each logical device. as an option, system resources can be reassigned at runtime with a plug and play resource manager. the custom setup created using the manager can be saved and used automatically on subsequent system boots. plug and play device ids (embedded in the logical devices resource data) provide the system with the information required to f ind and load the correct device drivers. one custom driver, the AD1821 sound system driver from analog devices, is required for cor - rect operation. in the other cases (midi, game port), the system can use generic drivers. table iii lists the AD1821s logical devices and compatible plug and play device drivers. table iii. logical devices and compatible plug and play device drivers logical device number emulated device compatible (device id) device id 0 sound system ads7180 1 midi mpu401 compatible pnpb006 ads7181 2 game/joystick port pnpb02f ads7182 the configuration process for the logical devices on the AD1821 is described in the plug and play isa specification version 1.0a (may 5, 1994 ). the specification describes how to transfer the logical devices from their start-up wait for key state to the config state and how to assign i/o ranges, interrupt channels and dma channels. see appendix a for an example setup program and specific plug and play resource data. table iv describes in detail the i/o port address descriptors, dma channels, interrupts for the functions required for the ad18 21 logical device groups.
AD1821 C22C rev. 0 table iv. logical device configuration ldn pnp function description 0 i/o port address descriptor (0x60-0x61) the soundblaster pro address range is from 0x100 to 0x3f0. the typical address is 0x220. the range is 16 bytes long and must be aligned to a 16 byte memory boundary. 0 i/o port address descriptor (0x62-0x63) the adlib address range is from 0x100 to 0x3f8. the typical address is 0x388. the range is 4 bytes long and must be aligned to an 8 byte memory boundary. 0 i/o port address descriptor (0x64-0x65) the codec address range is from 0x100 to 0x3f8. the range is 16 bytes long and must be aligned to a 16 byte memory boundary. 0 interrupt request level select (0x70-0x71) this irq is shared between the sb pro device and the codec. these devices require one of the following irq channels: 5, 7, 9, 11, 12 or 15. typically, the irq is set to 5 or 7 for this device. 0 dma playback channel select (0x74) this 8-bit channel is shared between the sb pro device and the codec for playback. these devices require one of the following dma chan- nels: 0, 1, 3. typically, dma channel 1 is set. 0 dma capture channel select (0x75) this the dma channel used for capturing codec data. the codec op- erates in single channel mode if a separate dma channel for capture and playback is not assigned. the following dma channels may be programmed: 0, 1, 3. dma channel 4 indicates single channel mode. 1 i/o port address descriptor (0x60-0x61) the mpu-401 compatible device address range is 0x100 to 0x3fe. typical configurations use 0x330. the range is 2 bytes long and must be aligned to a 2 byte memory boundary. 1 interrupt request level select (0x70-0x71) the midi device requires one of the following irq channels: 5, 7, 9, 11, 12 or 15. 2 i/o port address descriptor (0x60-0x61) the game port address range is from 0x100 to 0x3f8. the typical address is 0x200. the range is 8 bytes long and must be aligned to an 8 byte memory boundary. note dma channel 4 indicates single-channel mode. sound system direct registers the AD1821 has a set of 16 programmable sound system direct registers and 36 indirect registers. this section describes all the AD1821 registers and gives their address, name and initialization state/reset value. following each register table is a list (i n ascending order) of the full register name, its usage and its type: (ro) read only, (wo) write only, (stky) sticky, (rw) read write and reserved (res). table v is a map of the AD1821 direct registers. table v. sound system direct registers direct address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ssbase + 0 crdy vbl inadr[5:0] ssbase + 1 pi ci ti vi di ri gi si ssbase + 2 indirect ss data [7:0] ssbase + 3 indirect ss data [15:8] ssbase + 4 res pur cor orr [1:0] orl [1:0] ssbase + 5 pfh pdr plr pul cfh cdr clr cul ssbase + 6 pio playback/capture [7:0] ssbase + 7 reserved ssbase + 8 trd daz pfmt [1:0] pc/l pst pio pen ssbase + 9 res cfmt [1:0] pc/l cst cio cen ssbase + 10 reserved ssbase + 11 reserved ssbase + 12 joystick data [7:0] ssbase + 13 jrdy jwrp jsel [1:0] jmsk [3:0] ssbase + 14 jaxis [7:0] ssbase + 15 jaxis [15:8]
AD1821 C23C rev. 0 [base+0] chip/modem status/indirect address 76543210 crdy vbl inadr[5:0] reset = [0x00] inadr [5:0] (rw) indirect a ddress for sound system (ss). these bits are used to access the indirect registers shown in table viii. all registers data must be written in pairs, low byte followed by high byte, by loading the indirect ss data registers, (base+2) and (base+3). vbl volume button location. when using an eeprom to configure the pnp state of the AD1821, this bit determines whether pqfp pins 1 and 2 (tqfp pins 99 and 100) are used for vol_up and vol_dn or i2s0_data and i2s0_lrclk respectively. 0 i2s0_data and i2s0_lrclk 1 vol_up and vol_dn crdy (ro) AD1821 ready. the AD1821 asserts this bit when AD1821 can accept data. 0 AD1821 not ready 1 AD1821 ready [base+1] interrupt status 76543210 pi ci ti vi di ri gi si reset = [0x00] si (ro) soundblaster generated interrupt. 0 no interrupt 1 soundblaster interrupt pending gi (rw) game interrupt (sticky, write 0 to clear). 0 no interrupt 1 an interrupt is pending due to digital game port data ready ri (rw) ring interrupt (sticky, write 0 to clear). 0 no interrupt 1 an interrupt is pending due to a hardware ring pin being asserted di (rw) dsp interrupt (sticky, write 0 to clear). 0 no interrupt 1 an interrupt is pending due to a write to the dit bit in indirect register [33] bit <13> vi (rw) volume interrupt (sticky, write 0 to clear). 0 no interrupt 1 an interrupt is pending due to hardware volume button being pressed ti (rw) timer interrupt. this bit indicates there is an interrupt pending from the timer count registers. (sticky, write 0 to clear). 0 no interrupt 1 interrupt is pending from the timer count register ci (rw) capture interrupt. this bit indicates that there is an interrupt pending from the capture dma count register. (sticky, write 0 to clear). 0 no interrupt 1 interrupt is pending from the capture dma count register pi (rw) playback interrupt. this bit indicates that there is an interrupt pending from the playback dma count register. (sticky, write 0 to clear). 0 no interrupt 1 interrupt is pending from the playback dma count register [base+2] indirect ss data low byte 76543210 indirect ss data [7:0] reset = [0xxx] [base+3] indirect ss data high byte 76543210 indirect ss data [15:8] reset = [0xxx] indirect ss indirect sound system data. data in this register is written to the sound system indirect register specified by the data [15:0] address contained in indar [5:0], sound system direct register [base+0]. data is written when the indirect ss data high byte value is loaded.
AD1821 C24C rev. 0 [base+4] pio debug 76543210 res pur cor orr[1:0] orl[1:0] reset = [0x00] all bits in this register are sticky until any write that clears all bits to 0. orl/orr (ro) overrange left/right detect. these bits record the largest output magnitude on the adc right and left [1:0] channels and are cleared to 00 after any write to this register. the peak amplitude as recorded by these bits is sticky, i.e., the largest output magnitude recorded by these bits will persist until these bits are explicitly cleared. they are also cleared by powering down the chip. orl/orr over/under range detection 00 less than ? db underrange 01 between ? db and 0 db underrange 10 between 0 db and 1 db overrange 11 greater than 1 db overrange cor (ro) capture over run. the codec sets (1) this bit when capture data is not read within one sample period after the capture fifo fills. when cor is set, the fifo is full and the codec discards any new data generated. the codec clears this bit immediately after a 4 byte capture sample is read. pur (ro) playback under run. the codec sets (1) this bit when playback data is not written within one sample period af- ter the playback fifo empties. the codec clears (0) this bit immediately after a 4 byte playback sample is writ- ten. when pur is set, the playback channel has run out of data and either plays back a mid-scale value or repeats the last sample. [base+5] pio status 76543210 pfh pdr plr pul cfh cdr clr cul reset = [0x00] cul (ro) capture upper/lower sample. this bit indicates whether the pio capture data ready is for the upper or lower byte of the channel. 0 lower byte ready 1 upper byte ready or any 8-bit mode clr (ro) capture left/right sample. this bit indicates whether the pio capture data waiting is for the left channel adc or the right channel adc. 0 right channel 1 left channel or mono cdr (ro) c apture data ready. the pio capture data register contains data ready for reading by the host. this bit should be used only when direct programmed i/o data transfers are desired (fifo has at least 4 bytes before full). 0 adc is stale. do not reread the information 1 adc data is fresh. ready for next host data read cfh (ro) capture fifo half full. (fifo has at least 32 bytes before full.) pul (ro) playback upper/lower sample. this bit indicates whether the pio playback data needed is for the upper or lower byte of the channel. 0 lower byte needed 1 upper byte needed or any 8-bit mode plr (ro) playback left/right sample. this bit indicates whether the pio playback data needed is or the left channel dac or the right channel dac. 0 right channel needed 1 left channel or mono pdr (ro) playback data ready. the pio playback data register is ready for more data. this bit should only be used when direct programmed i/o data transfers are desired (fifo can take at least 4 bytes). 0 dac data is still valid. do not overwrite 1 dac data is stale. ready for next host data write value pfh (ro) playback fifo half empty. fifo can take at least 32-bytes, 8 groups of 4-bytes.
AD1821 C25C rev. 0 [base+6] pio data 76543210 pio playback/capture [7:0] reset = [0x00] pio playback/ the programmed i/o (pio) data registers for capture and playback are mapped to the same address. writes capture [7:0] send data to the playback register and reads will receive data from the capture register. reading this register will increment the capture byte state machine so that the following read will be from the next appropriate byte in the sample. the exact byte may be determined by reading the pio status register. once all relevant bytes have been read, the state machine will stay pointed to the last byte of the sample until a new sample is received. writing data to this register will increment the playback byte tracking state machine so that the following write will be to the correct byte of the sample. once all by tes have been written, subsequent byte writes will be ignored. the state machine is reset when the current sample is transferred. note: all writes to the fifo must contain 4 bytes of data. * 1 sample of 16-bit stereo * 2 samples of 16-bit mono * 2 samples of 8-bit stereo (linear pcm, m -law pcm, a-law pcm) * 4 samples of 8-bit mono (linear pcm, m -law pcm, a-law pcm) [base+7] reserved 76543210 reserved [7:0] reset = [0xxx] [base+8] playback configuration 76543210 trd daz pfmt [1:0] pc/l pst pio pen reset = [0x00] pen (rw) playback enable. this bit enables or disables programmed i/o data playback. 0 disable 1 enable pio (rw) programmed input/output. this bit determines whether the playback data is transferred via dma or pio. 0 dma transfers only 1 pio transfers only pst (rw) playback stereo/mono select. these bits select stereo or mono formatting for the input audio data streams. in stereo, the codec alternates samples between channels to provide left and right channel in- put. for mono, the codec cap tures samples on the left channel stereo. 0 mono 1 stereo pc/l (rw) playback companded/linear select. this bit selects between a linear digital representation of the audio signal or a nonlinear companded format for all output data. the type of linear pcm or the type of companded for- mat is defined by pfmt [1:0]. 0 linear pcm 1 companded pfmt [1:0] (rw) playback format. use these bits to select the playback data format for output data according to table vi and figure 15. daz (rw) dac zero. this bit forces the dac to zero. 0 repeat last sample 1 force dac to zero trd (rw) transfer request disable. this bit enables or disables codec dma transfers during a codec interrupt (indi- cated by the ss codec status registers int bit being set [1]). this assumes codec dma transfers were en- abled and the pen or cen bits are set. 0 transfer request enable 1 transfer request disable after setting format bits, sample data into the AD1821 must be ordered according to figure 15, table vi.
AD1821 C26C rev. 0 ior/iow pc_d [7:0] t bwdn byte n n + 1 n + 2 n + 3 figure 15. codec transfers table vi. codec transfers byte 3 byte 2 byte 1 byte 0 st fmt1 fmt0 c/l format msb lsb msb lsb msb lsb msb lsb 0 000 mono sample 3 sample 2 sample 1 sample 0 linear, 8-bit 8 bits 8 bits 8 bits 8 bits unsigned left channel left channel left channel left channel 1 000 stereo sample 1 sample 1 sample 0 sample 0 linear, 8-bit 8 bits 8 bits 8 bits 8 bits unsigned right channel left channel right channel left channel 0 001 mono sample 3 sample 2 sample 1 sample 0 m -law, 8-bit 8 bits 8 bits 8 bits 8 bits companded left channel left channel left channel left channel 1 001 stereo sample 1 sample 1 sample 0 sample 0 m -law, 8-bit 8 bits 8 bits 8 bits 8 bits companded right channel left channel right channel left channel 0 010 mono sample 1 sample 1 sample 0 sample 0 linear 16-bit upper 8 bits lower 8 bits upper 8 bits lower 8 bits little endian left channel left channel left channel left channel 1 010 stereo sample 0 sample 0 sample 0 sample 0 linear 16-bit upper 8 bits lower 8 bits upper 8 bits lower 8 bits little endian right channel right channel left channel left channel 0 011 mono sample 3 sample 2 sample 1 sample 0 a-law, 8-bit 8 bits 8 bits 8 bits 8 bits companded left channel left channel left channel left channel 1 011 stereo sample 1 sample 1 sample 0 sample 0 a-law, 8-bit 8 bits 8 bits 8 bits 8 bits companded right channel left channel right channel left channel 0 100 reserved 1 100 reserved 0 101 reserved 1 101 reserved 0 110 mono sample 1 sample 1 sample 0 sample 0 linear, 16-bit lower 8 bits upper 8 bits lower 8 bits upper 8 bits big endian left channel left channel left channel left channel 0 110 stereo sample 0 sample 0 sample 0 sample 0 linear, 16-bit lower 8 bits upper 8 bits lower 8 bits upper 8 bits big endian right+ channel left channel left channel left channel 0 111 reserved 1 111 reserved
AD1821 C27C rev. 0 [base+9] capture configuration 76543210 res cfmt [1:0] cc/l cst cio cen reset = [0x00] cen (rw) capture enable. this bit enables or disables data capture. 0 disable 1 enable cio (rw) capture programmed i/o. this bit determines whether the capture data is transferred via dma or pio. 0 dma 1 pio cst (rw) capture stereo/mono select. this bit selects stereo or mono formatting for the input audio data streams. in stereo, the codec alternates samples between channels to provide left and right channel input. for mono, the codec captures samples on the left channel. 0 mono 1 stereo cc/l (rw) capture companded/linear select. this bit selects between a linear digital representation of the audio sig- nal or a nonlinear, companded format for all output data. the type of linear pcm or the type of companded format is defined by cfmt [1:0]. 0 linear pcm 1 companded cfmt [1:0] (rw) capture format. use these bits to select the format for capture data according to the following table vi and figure 15. [base+10] reserved 76543210 reserved reset = [0xxx] [base+11] reserved 76543210 reserved reset = [0xxx] [base+12] joystick raw data 76543210 joystick data [7:0] reset = [0xf0] joystick data (ro) joystick data. joystick data (identical to 0x201): writes to this register are ignored. [base+13] joystick control 76543210 jrdy jwrp jsel [1:0] jmsk [3:0] reset = 0xf0 jmsk [3:0] (rw) joystick axis mask. jrdy bit calculated based on axes selected by jmsk only. xxx1 enable ax xx1x enable ay x1xx enable bx 1xxx enable by jsel [1:0] (rw) joystick select. selects one of four joystick axis register sets according to the following table: 00 read ax (16 bits) from [base+14] & [base+15] 01 read ay (16 bits) from [base+14] & [base+15] 10 read bx (16 bits) from [base+14] & [base+15] 11 read by (16 bits) from [base+14] & [base+15] jwrp (rw) joystick wrapmode. continuous joystick sampling modesampling automatically restarted every ~16 ms. jrdy (ro) joystick ready. sampling complete, joystick data ready for reading. note: sampling must be started manually if jwrp is set before any sampling cycles are run. to start sampling after setting the jwrp bit, write to the joystick port [base+14].
AD1821 C28C rev. 0 [base+14] joystick position data low byte 76543210 jaxis [7:0] reset = [0xff] jaxis [7:0] (ro) joystick axis low byte. note: axis to be read through this register is selected by the jsel bits in the control register. a write to this register start s a sampling cycle. [base+15] joystick position data high byte 76543210 jaxis [15:8] reset = [0xff] jaxis [15:8] (ro) joystick axis high byte. note: axis to be read through this register is selected by the jsel bits in the control register. a write to this register start s a sampling cycle. sound system indirect registers writing indirect registers all indirect registers must be written in pairs: low byte followed by high byte. the indirect address register [ssbase+0] holds the address for a register pair, the indirect low data byte [ssbase+2] is used to write low data byte and the indirect hi gh data byte [ssbase+3] is used to write the high data byte. the low data byte is held in the temporary register until the upper byte is written. programming example write sample rate for voice playback at 11,000 hz (0x2af8) 1) write [ssbase+0] with 0x02 ; indirect register for voice playback sample rate 2) write [ssbase+2] with 0xf8 ; low byte of 16-bit sample rate register 3) write [ssbase+3] with 0x2a ; high byte of 16-bit sample rate register reading indirect registers all indirect registers can be individually read. the sound system indirect address register [ssbase+0] holds the address for a reg- ister pair, the indirect low data byte [ssbase+2] is used to read low data byte and indirect high data byte [ssbase+3] is used to read the high data byte. programming example read sample rate for voice playback set to 11,000 hz (0x2af8) 1) write [ssbase+0] with 0x02 ; indirect register for voice playback sample rate 2) read [ssbase+2] ; low byte of 16-bit sample rate register set to 0xf8 3) read [ssbase+3] ; high byte of 16-bit sample rate register set to 0x2a isr saves and restores for interrupt service routines, isrs, it is necessary to save and restore the indirect address and the low byte temporary data holding registers inside the isr. programming example save/restore during an isr beginning of isr: 1) read [ssbase+0] ; save indirect address register to tmp_ia 2) write [ssbase+0] with 0x00; ; indirect register for low byte temporary data 3) read [ssbase+2] ; save low byte temporary data to tmp_lbt 4) isr code ; isr routine 5) write [ssbase+2] with tmp_lbt ; restore low byte temporary data tmp_lbt 6) write [ssbase+0] with tmp_ia ; restore indirect address register to tmp_ia 7) return from interrupt ; return from isr
AD1821 C29C rev. 0 table vii. indirect register map and reset/default states reset/ address register name default state 00 low byte tmp 0xxx 01 interrupt enable and external control 0x0102 02 voice playback sample rate 0x1f40 03 voice capture sample rate 0x1f40 04 voice attenuation 0x8080 05 fm attenuation 0x8080 06 i 2 s(1) attenuation 0x8080 07 i 2 s(0) attenuation 0x8080 08 playback base count 0x0000 09 playback current count 0x0000 10 capture base count 0x0000 11 capture current count 0x0000 12 timer base count 0x0000 13 timer current count 0x0000 14 master volume attenuation 0x0000 15 cd gain/attenuation 0x8888 16 synth gain/attenuation 0x8888 17 video gain/attenuation 0x8888 18 line gain/attenuation 0x8888 19 mic/phone-in gain/attenuation 0x8888 20 adc source select and adc pga 0x0000 32 chip configuration 0x00f0 33 dsp configuration 0x0000 34 fm sample rate 0x5622 35 i 2 s(1) sample rate 0xac44 36 i 2 s(0) sample rate 0xac44 37 reserved 0x0000 38 programmable clock rate 0xac44 39 3d phat? stereo control/phone_out gain attenuation 0x8000 40 reserved 0x0000 41 hardware volume button modifier 0xxx1b 42 dsp mailbox 0 0x0000 43 dsp mailbox 1 0x0000 44 power-down and timer control 0x0000 45 version id 0x0000 46 reserved 0x0000
AD1821 C30C rev. 0 table viii. sound system indirect registers (high byte) (low byte) address 7654321076543210 00 (0x00) res lbtd [7:0] 01 (0x01) pie cie tie vie die rie jie sie res xc1 xc0 02 (0x02) vpsr [15.8] vpsr [7:0] 03 (0x03) vcsr [15:8] vcsr [7:0] 04 (0x04) lvm res lva [5:0] rvm res rva [5:0] 05 (0x05) lfmm res lfma [5:0] rfmm res rfma [5:0] 06 (0x06) ls1m res ls1a [5:0] rs1m res rs1a [5:0] 07 (0x07) ls0m res ls0a [5:0] rs0m res rs0a [5:0] 08 (0x08) pbc [15:8] pbc [7:0] 09 (0x09) pcc [15:8] pcc [7:0] 10 (0x0a) cbc [15:8] cbc [7:0] 11 (0x0b) ccc [15:8] ccc [7:0] 12 (0x0c) tbc [15:8] tbc [7:0] 13 (0x0d) tcc [15:8] tcc [7:0] 14 (0x0e) lmvm res lmva [4:0] rmvm res rmva [4:0] 15 (0x0f) lcdm res lcda [4:0] rcdm res rcda [4:0] 16 (0x10) lsym res lsya [4:0] rsym res rsya [4:0] 17 (0x11) lvdm res lvda [4:0] rvdm res rvda [4:0] 18 (0x12) llm res lla [4:0] rlm res rla [4:0] 19 (0x13) mcm m20 res mca [4:0] pim res pia [3:0] res 20 (0x14) lagc las [2:0] lag [3:0] ragc ras [2:0] rag [3:0] 32 (0x20) wse cde res cnp res cof [3:0] i2sf1 [1:0] i2sf0 [1:0] 33 (0x21) ds1 ds0 dit res adr i1t i0t cpi pbi fmi i1i i01 dfs [2:0] 34 (0x22) fsmr [15:8] fmsr [7:0] 35 (0x23) s1sr [15:8] s1sr [7:0] 36 (0x24) s0sr [15:8] s0sr [7:0] 37 (0x25) res res 38 (0x26) pcr [15:8] pcr [7:0] 39 (0x27) 3ddm res 3dd [3:0] res pom res poa [4:0] 40 (0x28) res res 41 (0x29 ) res vmu vup vdn bm [4:0] 42 (0x2a) mb0r [15:8] mb0r [7:0] 43 (0x2b) mb1r [15:8] mb1r [7:0] 44 (0x2c) cpd res piw pir paa pda pdp ptb 3d pd3d gpsp res 45 (0x2d) ver [15:8] ver [7:0] 46 (0x2e) res res [00] indirect low byte tmp default = [0xxx] 7654321076543210 res lbtd [7:0] lbtd [7:0] low byte temporary data holding latch for register pair writes; written on any write to [ssbase + 2], read from [ssbase + 2] when the indirect address is 0x00. [01] interrupt enable and external control default = [0x0102] 7654321076 543210 pie cie tie vie die rie jie sie res xc1 xc0 xc0 rw external control 0. the state of this bit is reflected on the xctl0 pin. this pin is also muxed with pclko. cof must be greater than 11 for pclko to be disabled, see ss [32]. xc1 rw external control 1. the state of this bit is reflected on the xctl1 pin. xctl1 may also be used for ring-in interrupt. sie rw soundblaster interrupt enable; 0 soundblaster interrupt disabled 1 soundblaster interrupt enabled jie rw joystick interrupt enable; 0 joystick interrupt disabled 1 joystick interrupt enabled
AD1821 C31C rev. 0 rie rw ring interrupt enable; 0 ring interrupt disabled 1 ring interrupt enabled die rw dsp interrupt enable; 0 dsp interrupt disabled 1 dsp interrupt enabled vie rw volume interrupt enable. if enabled, software increments/decrements button modifier via interrupt routine and pushing buttons only sets vup, vdn, vmu bits. it does not change the volume. 0 volume interrupt disabled 1 volume interrupt enabled tie rw timer interrupt enable; 0 timer interrupt disabled 1 timer interrupt enabled cie rw capture interrupt enable; 0 capture interrupt disabled 1 capture interrupt enabled pie rw playback interrupt enable; 0 playback interrupt disabled 1 playback interrupt enabled [02] voice playback sample rate default = [0x1f40] 765432107654321 vpsr [15:8] vpsr [7:0] vpsr [15:0] voice p layback sample rate. the sample rate can be programmed from 4 khz to 55.2 khz in 1 hertz increments. the default playback sample rate is 8 khz. [03] voice capture sample rate default = [0x1f40] 7654321076543210 vcsr [15:8] vcsr [7:0] vcsr [15:0] voice capture sample rate. the sample rate can be programmed from 4 khz to 55.2 khz in 1 hertz increments. ignored if cnp bit in ss [32] = 0 in which case vpsr [15:0] controls capture rate. the default capture sample rate is 8 khz. [04] voice attenuation default = [0x8080] 7654321076543210 lvm res lva [5:0] rvm res rva [5:0] rva [5:0] right voice attenuation for playback channel. the lsb represents C1.5 db, 000000 = 0 db and the range is 0 db to C94.5 db. rvm right voice mute. 0 = unmuted, 1 = muted. lva [5:0] left voice attenuation for playback channel. the lsb represents C1.5 db, 000000 = 0 db and the range is 0 db to C94.5 db lvm left voice mute. 0 = unmuted, 1 = muted. [05] fm attenuation default = [0x8080] 7654321076543210 lfmm res lfma [5:0] rfmm res rfma [5:0] rfma [5:0] right f music attenuation for the internal music synthesizer. the lsb represents ?.5 db, 000000 = 0 db and the range is 0 db to ?4.5 db. rfmm right f music mute. 0 = unmuted, 1 = muted. lfma [5:0] left f music attenuation for the internal music synthesizer. the lsb represents ?.5 db, 000000 = 0 db and the range is 0 db to ?4.5 db. lfmm left f music mute. 0 = unmuted, 1 = muted. [06] i 2 s(1) attenuation default = [0x8080] 7654321076543210 ls1m res ls1a [5:0] rs1m res rs1a [5:0] rs1a [5:0] right i 2 s(1) attenuation register. the lsb represents C1.5 db, 000000 = 0 db and the range is 0 db to C94.5 db.
AD1821 C32C rev. 0 rs1m right i 2 s(1) mute. 0 = unmuted, 1 = muted. ls1a [5:0] left i 2 s(1) attenuation register. the lsb represents C1.5 db, 000000 = 0 db and the range is 0 db to C94.5 db. ls1m left i 2 s(1) mute. 0 = unmuted, 1 = muted. [07] i 2 s(0) attenuation default = [0x8080] 7654321076543210 ls0m res ls0a [5:0] rs0m res rs0a [5:0] rs0a [5:0] right i 2 s(0) attenuation register. the lsb represents C1.5 db, 000000 = 0 db and the range is 0 db to C94.5 db. rs0m right i 2 s(0) mute. 0 = unmuted, 1 = muted. ls0a [5:0] left i 2 s(0) attenuation register. the lsb represents C1.5 db, 000000 = 0 db and the range is 0 db to C94.5 db. ls0m left i 2 s(0) mute. 0 = unmuted, 1 = muted. [08] playback base count default = [0x0000] 7654321076543210 pbc [15:8] pbc [7:0] pbc [15:0] playback base count. this register is for loading the playback dma count. writing a value to this register also loads the same data into the playback current count register. you must load this register when playback enable (pen) is deasserted. when pen is asserted, the playback current count decrements once for every four bytes transferred via a dma cycle. the next transfer, after zero is reached in the playback current count, will generate an interrupt and reload the playback current count with the value in the playback base count. the playback base count should always be programmed to number bytes divided by four, minus one ((number bytes/4) C1). the circular software dma buffer must be divisible by four to ensure proper operation. [09] playback current count default = [0x0000] 7654321076543210 pcc [15:8] pcc [7:0] pcc [15:0] playback current count register. contains the current playback dma count. reads and writes must be done when pen is deasserted. [10] capture base count default = [0x0000] 7654321076543210 cbc [15:8] cbc [7:0] cbc [15:0] capture base count. this register is for loading the capture dma count. writing a value to this register also loads the same data into the capture current count register. loading must be done when capture enable (cen) is deasserted. when cen is asserted, the capture current count decrements once for every four bytes transferred via a dma cycle. the next transfer, after zero is reached in the capture current count, will generate an interrupt and reload the capture current count with the value in the capture base count. the capture base count should always be programmed to number bytes divided by four, minus one ((number bytes/4) C1). the circular software dma buffer must be divisible by four to ensure proper operation. [11] capture current count default = [0x0000] 7654321076543210 ccc [15:8] ccc [7:0] ccc [15:0] capture current count register. contains the current capture dma count. reading and writing must be done when cen is deasserted. [12] timer base count default = [0x0000] 7654321076543210 tbc [15:8] tbc [7:0] tbc [15:0] timer base count. register for loading the timer count. writing a value to this register also loads the same data into the timer current count register. loading must be done when timer enable (te) is deasserted. when te is asserted, the timer current count register decrements once for every specified time period. the time period (10 m s or 100 ms) is programmed via the ptb bit in ss [44]. when te is asserted, the timer current count decrements once every time period. the next count, after zero is reached in the timer current count register, will generate an interrupt and reload the timer current count register with the value in the timer current count register.
AD1821 C33C rev. 0 [13] timer current count default = [0x0000] 7654321076543210 tcc [15:8] tcc [7:0] tcc [15:0] timer dma current count register. contains the current timer count. reading and writing must be done when te is deasserted. [14] master volume attenuation default = [0x0000] 7654321076543210 lmvm res lmva [4:0] rmvm res rmva [4:0] rmva [4:0] right master volume attenuation. the lsb represents C1.5 db, 00000 = 0 db and the range is 0 db to C46.5 db. this register is added with the hardware volume button modifier value to produce the final dac master volume attenuation level. see hardware volume button modifier register description for more details. rmvm right master volume mute. 0 = unmuted, 1 = muted. lmva [4:0] left master volume attenuation. the lsb represents C1.5 db, 00000 = 0 db and the range is 0 db to C46.5 db. this register is added with the hardware volume button modifier value to produce the final dac master volume attenuation level. see hardware volume button modifier register description for more details. lmvm left master volume mute. 0 = unmuted, 1 = muted. [15] cd gain/attenuation default = [0x8888] 7654321076543210 lcdm res lcda [4:0] rcdm res rcda [4:0] rcda [4:0] right cd attenuation. the lsb represents C1.5 db, 00000 = +12 db and the range is +12 db to C34.5 db. rcdm right cd mute. 0 = unmuted, 1 = muted. lcda [4:0] left cd attenuation. the lsb represents C1.5 db, 00000 = +12 db and the range is +12 db to C34.5 db. lcdm left cd mute. 0 = unmuted, 1 = muted. [16] synth gain/attenuation default = [0x8888] 7654321076543210 lsym res lsya [4:0] rsym res rsya [4:0] rsya [4:0] right synth attenuation. the lsb represents C1.5 db, 00000 = +12 db and the range is +12 db to C34.5 db. rsym right synth mute. 0 = unmuted, 1 = muted. lsya [4:0] left synth attenuation. the lsb represents C1.5 db, 00000 = +12 db and the range is +12 db to C34.5 db. lsym left synth mute. 0 = unmuted, 1 = muted. [17] vid gain/attenuation default = [0x8888] 7654321076543210 lvdm res lvda [4:0] rvdm res rvda [4:0] rvda [4:0] right vid attenuation. the lsb represents C1.5 db, 00000 = +12 db and the range is +12 db to C34.5 db. rvdm right vid mute. 0 = unmute, 1 = muted. lvda [4:0] left vid attenuation. the lsb represents C1.5 db, 00000 = +12 db and the range is +12 db to C34.5 db. lvdm left vid mute. 0 = unmuted, 1 = muted. [18] line gain/attenuation default = [0x8888] 7654321076543210 llm res lla [4:0] rlm res rla [4:0] rla [4:0] right line attenuation. the lsb represents C1.5 db, 00000 = +12 db and the range is +12 db to C34.5 db. rlm right line mute. 0 = unmuted, 1 = muted. lla [4:0] left line attenuation. the lsb represents C1.5 db, 00000 = +12 db and the range is +12 db to C34.5 db. llm left line mute. 0 = unmuted, 1 = muted.
AD1821 C34C rev. 0 [19] mic/phone_in gain/attenuation default = [0x8888] 7654321076543210 mcm m20 res mca [4:0] pim res pia [3:0] res pia [3:0] phone_in attenuation. the lsb represents C3 db, 0000 = 0 db and the range is 0 db to C45 db. pim phone_in mute. mca [4:0] microphone attenuation. the lsb represents C1.5 db, 00000 = +12 db and the range is 12 db to C34.5 db. m20 microphone 20 db gain. the m20-bit enables the microphone +20 db gain stage. mcm microphone mute. [20] adc source select and adc pga default = [0x0000] 7654321076543210 lagc las [2:0] lag [3:0] ragc ras [2:0] rag [3:0] rag [3:0] right adc gain control adc source select and gain. for gain, lsb rep resents +1.5 db, 0000 = 0 db and the range is 0 db to +22.5 db. ragc right automatic gain control (agc) enable, 0 = enabled, 1 = disabled. lag [3:0] left adc gain control adc source select and gain. for gain, lsb rep resents +1.5 db, 0000 = 0 db and the range is 0 db to +22.5 db. lagc left automatic gain control (agc) enable, 0 = enabled, 1 = disabled. ras [2:0] adc right input source las [2:0] adc left input source 000 r_line 000 l_line 001 r_out 001 l_out 010 r_cd 010 l_cd 011 r _synth 011 l_synth 100 r _vid 100 l_vid 101 mono mix 101 mic 110 reserved 110 phone_in 111 reserved 111 reserved [32] chip configuration default = [0x00f0] 7654321076543210 wse cde res cnp res ime imr cof [3:0] i 2 sf1 [1:0] i 2 sf0 [1:0] i 2 sf0 [1:0] i 2 s port configuration for serial data type. i 2 sf1 [1:0] 00 disabled 01 right justified 10 i 2 s justified 11 left justified cof [3:0] clock output frequency. programmable clock output on pclko pin is determined using the following formula pclko = 256 pcr/2 cof where cof = 0:11 and pcr is the value of the programmable clock rate register, ss [38]. if cof > 11, then pclko is disabled. cnp capture not equal to playback. 0 = capture equals playback. the capture sample rate is determined by the playback sample rate in ss [02]. 1 = capture not equal to playback. cde cd enable, set to 1 when a cd player is connected to i 2 s (0). wse sound system enable. 0 = soundblaster mode. 1 = sound system mode under windows. note: when in soundblaster mode, the codec adc and dac channels will be used solely for converting soundblaster data.
AD1821 C35C rev. 0 [33] dsp configuration default = [0x0000] 7654321076543210 ds1 ds0 dit res adr i1t i0t cpi pbi fmi i1i i0i dfs [2:0] dfs [2:0] dsp frame sync source. sets the dsp port frame sync according to the following source. 000maximum frame rate 001i 2 s(0) sample rate 010i 2 s(1) sample rate 011music synthesizer sample rate 100sound system playback sample rate 101sound system capture sample rate 111reserved i0i i 2 s(0) data intercept. 0 = disable, 1 = intercept i 2 s(0) data enabled. i1i i 2 s(1) data intercept. 0 = disable, 1 = intercept i 2 s(1) data enabled. fmi fm music synthesizer data intercept. 0 = disable, 1 = intercept fm music data enabled. pbi playback data intercept. 0 = disable, 1 = intercept playback data enabled. cpi capture data intercept. 0 = disable, 1 = intercept capture data enabled. i0t i 2 s(0) takeover data. 0 = disable, 1 = enabled. i1t i 2 s(1) takeover data. 0 = disable, 1 = enabled. adr audio resync. writing 1 causes all fifos in the dsp port to be re-initialized. dit dsp interrupt. a write to this bit causes an isa interrupt if die is asserted. ds0 dsp mailbox 0 status. 0 = last access indicates read, 1 = last access indicates write. ds1 dsp mailbox 1 status. 0 = last access indicates read, 1 = last access indicates write. [34] fm sample rate default = [0x5622] 7654321076543210 fmsr [15:8] fmsr [7:0] fmsr [15:0] f music sample rate register. the sample rate can be programmed from 4 khz to 27.6 khz in 1 hertz increments. [35] i 2 s(1) sample rate default = [0xac44] 7654321076543210 s1sr [15:8] s1sr [7:0] s1sr [15:0] i 2 s(1) sample rate register. the sample rate can be programmed from 4 khz to 55.2 khz in 1 hertz increments. programming this register has no effect unless i 2 sf1 [1:0] is enabled. [36] i 2 s(0) sample rate default = [0xac44] 7654321076543210 s0sr [15:8] s0sr [7:0] s0sr [15:0] i 2 s(0) sample rate register. the sample rate can be programmed from 4 khz to 55.2 khz in 1 hertz increments. programming this register has no effect unless i 2 sf0 [1:0] is enabled. [37] reserved default = [0x0000] 7654321076543210 res res [38] programmable clock rate default = [0xac44] 7654321076543210 pcr [15:8] pcr [7:0] pcr [15:0] programmable clock rate register. the clock rate can be programmed from 25 khz to 50 khz in 1 hertz increments. this register is only valid when the cof bits in ss [32] are set for the multiplier factor. pclko = 256 pcr/2 cof . see ss [32] for determining the value of cof. [39] 3d phat stereo control and phone _out attenutation default = [0x8000] 7654321076543210 3ddm res 3dd [3:0] res pom res poa [4:0] poa [4:0] phone_out attenuation. the lsb represents C1.5 db, 0000 = 0 db and the range is 0 db to C46.5 db.
AD1821 C36C rev. 0 pom phone-out mute. 0 = unmuted, 1 = muted. 3dd [3:0] 3d depth phat? stereo enhancement control. the lsb represents 6 2/3% phase expansion, 0000 = 0% and the range is 0% to 100%. 3ddm 3d depth mute. writing a 1 to this bit has the same affect as writing 0s to 3dd [3:0] bits, and causes the phat? 3d stereo enhancement to be turned off. 0 = phat?* stereo is on, 1 = phat? stereo is off. [40] reserved default = [0x0000] 7654321076543210 res res [41] hardware volume button modifier default = [0xxx1b] 7654321076543210 res vmu vup vdn bm [4:0] bm [4:0] button modifier vdm volume down vup volume up vmu volume mute this register contains a master volume attenuation offset, which can be incremented or decremented via the hardware volume pins. this register is summed with the master volume attenuation to produce the actual master volume dac attenuation. a mo- mentary grounding of greater than 50 ms on the vol_up pin will cause a decrement (decrease in attenuation) in this register. holding the pin lo for greater than 200 ms will cause an auto-decrement every 200 ms. this is also true for a momentary ground- ing of the vol_dn pin. a momentary grounding of both the vol_up and vol_dn causes a mute and no increment or decre- ment to occur. when muted, an unmute is possible by a momentary grounding of both the vol_up and vol_dn pins together, a momen- tary grounding of vol_up (this also causes a volume increase), a momentary grounding of vol_dn (this also causes a volume decrease) or a write of 0 to the vi bit in ss [base+1]. [42] dsp mailbox 0 default = [0x0000] 7654321076543210 mb0r [15:8] mb0r [7:0] mb0r [15:0] this register is used to send data and control information to and from the dsp. [43] dsp mailbox 1 default = [0x0000] 7654321076543210 mb1r [15:8] mb1r [7:0] mb1r [15:0] this register is used to send data and control information to and from the dsp. [44] power-down and timer control default = [0x0000] 7654321076543210 cpd res piw pir paa pda pdp ptb 3d pd3d gpsp res the AD1821 supports a timeout mechanism used in conjunction with the timer base count and timer current count registers to generate a power-down interrupt. this interrupt allows software to power down the entire chip by setting the cpd bit. this power-down control feature lets users program a time interval from 1 ms to approximately 1.8 hours in 1 ms increments. five power-down count reload enable bits are used to reload the timer current count from the timer base count when activity is seen on that particular channel. programming example: generate interrupt if no isa reads or writes occur within 15 minutes. 1) write [ssbase+0] with 0x0c ; write indirect address for timer base count register 12 2) write [ssbase+2] with 0x28 ; write timer base count with (15 min 60 sec/min 10) = 0x2328 mili-seconds 3) write [ssbase+3] with 0x23 ; write high byte of timer base count 4) write [ssbase+0] with 0x2c ; write indirect address for power-down and timer control register 5) write [ssbase+2] with 0x00 ; write low byte of power-down and timer control register 6) write [ssbase+3] with 0x30 ; set enable bits for piw & pir 7) write [ssbase+0] with 0x01 ; write indirect address for interrupt config register 8) write [ssbase+2] with 0x82 ; set the te (timer enable) bit 9) write [ssbase+3] with 0x20 ; set the tie (timer interrupt enable) bit
AD1821 C37C rev. 0 gpsp game port speed select. selects the operating speed of the game port. 0 slow game port 1 fast game port pd3d power-down 3d. turns off internal phat? stereo circuitry. 0on 1 off 3d 3d analog mixer bypass. allows the analog output of the d/a converters to bypass the phat? stereo circuit. enables ultimate flexibility for mixing and any combination of 3d enhanced analog signals or non-3d enhanced signals with the dac output. 0 3d phat? stereo enabled for dac output 1 3d phat? stereo bypassed for dac output ptb power-down time base. 1 = timer set to 100 ms, 0 = timer set to 10 m s. pdp power-down count reload on dsp port enabled; 1 = reload count if dsp port enabled. dsp port is enabled when slot 0 of sdi of the dsp serial port input is alive (bit 7 = 1). pda power-down count reload on digital activity; 1 = reload count on digital activity. digital activity is defined as any activity on (i 2 s0, i 2 s1, fm or playback). paa power-down count reload on analog activity; 1 = reload count on analog activity. analog activity is defined as any analog input unmuted (line, cd, synth, mic, mono) or master volume unmuting. pir power-down count reload on isa read; 1 = reload count on isa read. isa read is defined as a read from any active logical device inside the AD1821. piw power-down count reload on isa write; 1 = reload count on isa write. isa write defined as a write to any active logical device inside the AD1821. cpd chip power-down 1 power-down; 0 power-up for power-up, software should poll the [ssbase+0] cry bit for 1 before writing or reading any logical device. [45] version id default = [0x0000] 7654321076543210 ver [15:8] ver [7:0] [46] reserved default = [0x0000] 7654321076543210 res res test register. should never be written or read under normal operation. sb pro; adlib registers the AD1821 contains sets of isa bus registers (ports) that correspond to those used by the soundblaster pro audio card from creative labs and the adlib audio card from adlib multimedia. table ix lists the isa bus soundblaster pro registers. table x lists the isa bus adlib registers. because the adlib registers are a su bset of those in the soundblaster card, you can find complete information on using both of these registers in the developer kit for soundblaster series, 2nd ed. ? 1993 , creative labs, inc., 1901 mccarthy blvd., milpitas, ca 95035. table ix. soundblaster pro isa bus registers register name isa bus address music0: address (w), status (r) 0x(sb base) relocatable in range 0x010 C 0x3f0 music0: data (w) 0x(sb base+1) music1: address (w) 0x(sb base+2) music1: data (w) 0x(sb base+3) mixer address (w) 0x(sb base+4) mixer data (w) 0x(sb base+5) reset (w) 0x(sb base+6) music0: address (w) 0x(sb base+8) music0: data (w) 0x(sb base+9) input data (r) 0x(sb base+a) status (r), output data (w) 0x(sb base+c) status (r) 0x(sb base+e)
AD1821 C38C rev. 0 table x. adlib isa bus registers register name isa bus address music0: address (w), status (r) 0x(adlib base) relocatable in range 0x008 C 0x3f8 music0: data (w) 0x(adlib base+1) music1: address (w) 0x(adlib base+2) music1: data (w) 0x(adlib base+3) midi and mpu-401 registers the AD1821 contains a set of isa bus registers (ports) that correspond to those used by the isa bus midi audio interface cards. table xi lists the isa bus midi registers. these registers support commands and data transfers described in midi 1.0 detailed specification and standard midi files 1.0, ? 1994, midi manufacturers association, po box 3173 la habra, ca 90632-3173. table xi. midi isa bus registers register name address midi data (r/w) 0x(midi base) relocatable in range 0x008 to 0x3f8 midi status (r), command (w) 0x(midi base+1) 0x(midi base+1) bit 76543210 state 10000000 name drr dsr reserved dsr (r) data send ready. when read, this bit indicates that you can (0) or cannot (1) write to the midi data register. (full = 1, empty = 0) drr (r) data receive ready. when read, this bit indicates that you can (0) or cannot (1) read from the midi data register. (unreadable = 1, readable = 0) cmd [7:0] (w) midi command. write mpu-401 commands to bits [7:0] of this register. notes the AD1821 supports only the midi 0xff (reset) and 0x3f (pass-through mode) commands. the controller powers setup for intel- ligent midi mode, but must be put in pass-through mode. to start midi operations, send a reset command (0xff) and then send a pass-through mode command (0x3f). the midi data register contains an acknowledge byte (0xfe) after each command transfer. all commands return an ack byte in smart mode. status commands (0xax) return ack and a data byte; all other commands return ack. all commands except reset (0xff) are ignored in uart mode. no ack bytes are returned. smart mode data transfers are not supported. game port registers the AD1821 contains a game port isa bus register that corresponds to the game port described in the pnp specification. table xii. game port isa bus registers register name address game port i/o 0x(game port base+0 to game port base+7 relocatable in the range 0x100 to 0x3f8
AD1821 C39C rev. 0 appendix a AD1821js and AD1821js-m contains the internal rom code on the AD1821js. consult the reference design guide for external eeprom code. AD1821js plug and play internal rom note: all addresses are depicted in hexidecimal notation. vendor id: ads7180 serial number: ffffffff checksum: b6 pnp version: 1.0, vendor version: 11 ascii string: analog devices logical device id: ads7180 not a boot device, implements pnp register(s) 31 start dependent function, best config irq: channel(s) 5 7 type(s) active-high, edge-triggered dma: channel(s) 1 type f, count-by-byte, nonbus-mastering, 8-bit only dma: channel(s) 0 1 3 type f, count-by-byte, nonbus-mastering, 8-bit only i/o: 16-bit decode, range [0220,0240] mod 20, length 10 i/o: 16-bit decode, range [0388,0388] mod 08, length 04 i/o: 16-bit decode, range [0500,0560] mod 10, length 10 start dependent function, acceptable config irq: channel(s) 5 7 10 type(s) active-high, edge-triggered dma: channel(s) 0 1 3 type f, count-by-byte, nonbus-mastering, 8-bit only dma: channel(s) 0 1 3 type f, count-by-byte, nonbus-mastering, 8-bit only i/o: 16-bit decode, range [0220,0240] mod 20, length 10 i/o: 16-bit decode, range [0388,0388] mod 08, length 04 i/o: 16-bit decode, range [0500,0560] mod 10, length 10 start dependent function, acceptable config irq: channel(s) 5 7 9 10 11 15 type(s) active-high, edge-triggered dma: channel(s) 0 1 3 type f, count-by-byte, nonbus-mastering, 8-bit only dma: channel(s) 0 1 3 type f, count-by-byte, nonbus-mastering, 8-bit only i/o: 16-bit decode, range [0220,02e0] mod 20, length 10 i/o: 16-bit decode, range [0388,03b8] mod 08, length 04 i/o: 16-bit decode, range [0500,0560] mod 10, length 10 start dependent function, suboptimal config irq: channel(s) 5 7 10 type(s) active-high, edge-triggered dma: channel(s) 0 1 3 type f, count-by-byte, nonbus-mastering, 8-bit only dma: null i/o: 16-bit decode, range [0220,02e0] mod 20, length 10 i/o: 16-bit decode, range [0388,03b8] mod 08, length 04 i/o: 16-bit decode, range [0500,0560] mod 10, length 10 end all dependent functions logical device id: ads7181 not a boot device, implements pnp register(s) 31 compatible device id: pnpb006 start dependent function, best config irq: channel(s) 5 7 9 11 type(s) active-high, edge-triggered i/o: 16-bit decode, range [0300,0330] mod 30, length 02 start dependent function, acceptable config irq: channel(s) 5 7 9 10 11 15 type(s) active-high, edge-triggered i/o: 16-bit decode, range [0300,0420] mod 30, length 02 end all dependent functions logical device id: ads7182 not a boot device, implements pnp register(s) 31 compatible device id: pnpb02f start dependent function, best config i/o: 16-bit decode, range [0200,0200] mod 08, length 08 start dependent function, acceptable config i/o: 16-bit decode, range [0200,0208] mod 08, length 08 end all dependent functions end:
AD1821 C40C rev. 0 contains the internal rom code on the AD1821js-m. consult the reference design guide for external eeprom code. AD1821js-m plug and play internal rom vendor id: ads7181 serial number: ffffffff checksum: 2f pnp version: 1.0, vendor version: 20 ascii string: analog devices logical device id: ads7180 not a boot device, implements pnp register(s) 31 start dependent function, best config irq: channel(s) 5 7 type(s) active-high, edge-triggered dma: channel(s) 1 type f, count-by-byte, nonbus-mastering, 8-bit only dma: channel(s) 0 1 3 type f, count-by-byte, nonbus-mastering, 8-bit only i/o: 16-bit decode, range [0220,0240] mod 20, length 10 i/o: 16-bit decode, range [0388,0388] mod 08, length 04 i/o: 16-bit decode, range [0500,0560] mod 10, length 10 start dependent function, acceptable config irq: channel(s) 5 7 10 type(s) active-high, edge-triggered dma: channel(s) 0 1 3 type f, count-by-byte, nonbus-mastering, 8-bit only dma: channel(s) 0 1 3 type f, count-by-byte, nonbus-mastering, 8-bit only i/o: 16-bit decode, range [0220,0240] mod 20, length 10 i/o: 16-bit decode, range [0388,0388] mod 08, length 04 i/o: 16-bit decode, range [0500,0560] mod 10, length 10 start dependent function, acceptable config irq: channel(s) 5 7 9 10 11 15 type(s) active-high, edge-triggered dma: channel(s) 0 1 3 type f, count-by-byte, nonbus-mastering, 8-bit only dma: channel(s) 0 1 3 type f, count-by-byte, nonbus-mastering, 8-bit only i/o: 16-bit decode, range [0220,02e0] mod 20, length 10 i/o: 16-bit decode, range [0388,03b8] mod 08, length 04 i/o: 16-bit decode, range [0500,0560] mod 10, length 10 start dependent function, suboptimal config irq: channel(s) 5 7 9 10 11 15 type(s) active-high, edge-triggered dma: channel(s) 0 1 3 type f, count-by-byte, nonbus-mastering, 8-bit only dma: null i/o: 16-bit decode, range [0220,02e0] mod 20, length 10 i/o: 16-bit decode, range [0388,03b8] mod 08, length 04 i/o: 16-bit decode, range [0500,0560] mod 10, length 10 end all dependent functions logical device id: ads7181 not a boot device, implements pnp register(s) 31 compatible device id: pnpb006 start dependent function, best config irq: channel(s) 5 7 9 11 type(s) active-high, edge-triggered i/o: 16-bit decode, range [0300,0330] mod 30, length 02 start dependent function, acceptable config irq: channel(s) 5 7 9 10 11 15 type(s) active-high, edge-triggered i/o: 16-bit decode, range [0300,0420] mod 30, length 02 end all dependent functions logical device id: ads7182 not a boot device, implements pnp register(s) 31 compatible device id: pnpb02f start dependent function, best config i/o: 16-bit decode, range [0200,0200] mod 08, length 08 start dependent function, acceptable config i/o: 16-bit decode, range [0200,0208] mod 08, length 08 end all dependent functions end:
AD1821 C41C rev. 0 appendix b plug and play key and alternate key sequences one additional feature of the AD1821 is an alternate programming method used, for example, if a bios wants to assume control of the AD1821 and present devnodes to the os (rather than having the device participate in plug and play enumeration). the fol- lowing technique may be used. instead of the normal 32 byte plug and play key sequence, an alternate 126 byte key is used. after the 126 byte key, the ad182 1 device will transition to the plug and play config state. it can then be programmed as usual using the standard plug and play ports. after programming, the AD1821 should be sent to the plug and play wfk (wait for key) state. once the AD1821 has seen the al- ternate key, it will no longer parse for the plug and play key (and therefore never participate in plug and play enumeration). it can be reprogrammed by reissuing the alternate key again. both the plug and play key and the alternate key are sequences of writes to the plug and play address register, 0x279. below ar e the isa data values of both keys. this is the standard plug and play sequence: 6a b5 da ed f6 fb 7d be df 6f 37 1b 0d 86 c3 61 b0 58 2c 16 8b 45 a2 d1 e8 74 3a 9d ce e7 73 39 this is the longer, 126-byte alternate key. it is generated by the function: f[n+1] = (f[n] >> 1)| (((f[n] ^ (f[n] >> 1)) & 0x01) << 6) f[0] = 0x01 01 40 20 10 08 04 02 41 60 30 18 0c 06 43 21 50 28 14 0a 45 62 71 78 3c 1e 4f 27 13 09 44 22 51 68 34 1a 4d 66 73 39 5c 2e 57 2b 15 4a 65 72 79 7c 3e 5f 2f 17 0b 05 42 61 70 38 1c 0e 47 23 11 48 24 12 49 64 32 59 6c 36 5b 2d 56 6b 35 5a 6d 76 7b 3d 5e 6f 37 1b 0d 46 63 31 58 2c 16 4b 25 52 69 74 3a 5d 6e 77 3b 1d 4e 67 33 19 4c 26 53 29 54 2a 55 6a 75 7a 7d 7e 7f 3f 1f 0f 07
AD1821 C42C rev. 0 programming external eeproms the pnp eeprom can be written only in the alternate key state; this prevents accidental eeprom erasure when using stan- dard pnp setup. the procedure for writing an eeprom is: 1) enter pnp configuration state and fully reset the part by writing 0x07 to pnp register 0x02. this step can be eliminated if the part has not been accessed since power-up, a previous full pnp reset or assertion of the isa bus reset signal. 2) send the alternate initiation key to the pnp address port. eeprom writes are disabled if the standard pnp key is used. 3) enter isolation state and write a csn to enter configuration state. do not perform any isolation reads. 4) poll pnp register 0x05 until it equals 0x01 and wait at least 336 microseconds (ensures that eeprom is idle). 5) write the second byte of your serial identifier to pnp register 0x20. 6) read pnp register 0x04. 7) wait for at least 464 microseconds, plus the eeproms write cycle time (up to 10 ms for a xicor x24c02). 8) repeat steps 4 through 7 for each byte in your pnp rom, starting with the third byte of the serial identifier and ending with the final checksum byte. you must then continue to write filler bytes until 512 bytes, minus one more than the number of flag byte s, have been written. finally, write the flag byte(s) (described above) and the first byte of the serial identifier. 9) fully reset the part by writing 0x07 to pnp register 0x02. the AD1821 will now act according to the contents of the eeprom. notes programming will not work if more than one part uses the same alternate initiation key in the system. if a 256-byte eeprom is used, it is not necessary to wait 10 ms after writing bytes 255 to 511, because the eeprom will ignore them anyway. you can skip over bytes that you dont care to write by just performing a rom read instead of a rom write followed by a rom rea d. reference designs and device drivers reference designs and device drivers for the AD1821 are available via the analog devices home page on the world wide web at http://www.analog.com. refe rence designs may also be obtained by contacting your local analog devices sales representat ive or authorized distributor.
AD1821 C43C rev. 0 xf s 0 ?00 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?10 0 0.8 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.9 1 db a. adc audio/modem xf s 0 ?.1 ?.2 0 0.1 db 0.2 0.3 0.4 b. adc audio/modem passband figure 16. AD1821 frequency response plots (full-scale line-level input, 0 db gain). the plots do not reflect the additional benefits of the on-chip analog filters. out-of-band images will be attenuated by an additional 31.4 db at 100 khz. xf s 0 ?00 08 1234567 ?0 ?0 ?20 ?60 ?80 ?0 ?0 ?00 ?40 db c. dac audio/modem xf s 0 ?.1 ?.2 0 0.1 db 0.2 0.3 0.4 d. dac audio/modem passband
AD1821 C44C rev. 0 c3057C12C7/97 printed in u.s.a. outline dimensions dimensions shown in inches and (mm). 100-lead plastic quad flatpack (s-100) 81 100 1 50 80 31 30 51 top view (pins down) pin 1 0.015 (0.35) 0.009 (0.25) 0.923 (23.45) 0.903 (22.95) 0.742 (18.85) typ 0.791 (20.10) 0.783 (19.90) 0.687 (17.45) 0.667 (16.95) 0.486 (12.35) typ 0.555 (14.10) 0.547 (13.90) 0.029 (0.73) 0.023 (0.57) seating plane 0.096 (2.45) max 0.037 (0.95) 0.026 (0.65) 0.004 (0.10) max 0.010 (0.25) min 0.083 (2.10) 0.075 (1.90)

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